Backside Power Rail Structure for Nano-FET Isolation and Density
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area while maintaining performance, including issues with electrical resistance and gate-to-power rail short circuiting.
Innovation Solution
The formation of a power rail on the backside of nano-FETs with a dielectric layer insulating it from channel regions, allowing for a wider power rail width and increased interconnect density, and the use of a gate-last process to enhance gate and channel region isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but electrical resistance increases and short circuiting risks arise
Solution Approach 1:
The power rail is moved from the front side to the back side of the semiconductor device, utilizing the third dimension (depth/thickness) to resolve spatial conflicts. This allows the power rail to be positioned behind the interconnect structure, eliminating interference with front-side signal routing while maintaining electrical connectivity through vertical vias. The backside positioning enables wider power rail dimensions without compromising front-side integration density.
Solution Approach 2:
The device is divided into distinct functional zones: front side for high-density interconnect and signal routing, back side for power delivery. The interconnect structure is segmented into front-side components (signal lines, vias) and back-side components (power rail, ground connections), allowing each to be optimized independently for its specific function without interference.
2Reliability
If power rail width is increased to reduce electrical resistance, then power delivery improves, but device area increases
Solution Approach 1:
The power rail is positioned on the back side of the device, allowing it to extend in lateral dimensions without occupying valuable front-side interconnect area. The backside location provides additional spatial freedom, enabling the power rail to achieve greater width and area for reduced resistance while the front side maintains its compact, high-density interconnect layout.
3Manufacturing precision
If gate-last process is used to improve gate and channel isolation, then manufacturing precision improves, but process complexity increases
Solution Approach 1:
The gate structure is formed last in the manufacturing sequence, after all other critical structures (interconnect, power rail, channel regions) are already in place. This preliminary positioning of the gate allows for precise alignment and isolation control, as the gate can be deposited and patterned with reference to previously formed structures, ensuring accurate gate-to-channel alignment without the complexity of multiple re-alignment steps.
Data Source
AI summary
Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.