Nano-FET Gate Capping Layers for Threshold Voltage Uniformity

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, challenges arise in maintaining uniformity and preventing the merging of capping materials around nanosheets, leading to variations in threshold voltage and device performance.

Innovation Solution

A method is employed where a first capping material is formed around the work function material of a nanosheet, followed by a second capping material that wraps around the first, ensuring a uniform thickness and preventing merging, thereby improving device performance by reducing threshold voltage variation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a single capping material is formed around the work function material, then the manufacturing process is simple, but the thickness uniformity deteriorates and merging occurs between adjacent nanosheets

Engineering Contradiction:

Improvecapping material deposition processVSAvoidcapping material thickness uniformity

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The capping material is divided into multiple separate layers (first capping material layer and second capping material layer) deposited at different times and orientations. This segmentation prevents the merging of capping materials between adjacent nanosheets while maintaining thickness uniformity, as each layer is deposited independently and can be controlled separately to avoid coalescence issues.

Inventive Principle:

Principle #1Segmentation

2Productivity

If feature size is reduced to increase integration density, then more components can be integrated, but threshold voltage variation increases due to capping material merging

Engineering Contradiction:

Improveintegration densityVSAvoidthreshold voltage uniformity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

By segmenting the capping material into multiple deposited layers, the patent prevents merging between adjacent nanosheets even at reduced feature sizes. This maintains consistent electrical characteristics and threshold voltage across devices, enabling higher integration density without sacrificing reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first capping material layer is deposited preliminary to provide initial coverage and protection, followed by the second layer to complete the capping structure. This preliminary action ensures that each nanosheet is properly capped before adjacent structures are formed, preventing merging and maintaining voltage uniformity at scaled dimensions.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250301731A1Gate structures of nanostructure field-effect transistors (nano-FETS) including a plurality of semiconductor based capping materials and methods

Publication Date: 2025.09.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes nanosheets between the source/drain regions, and a gate structure over the substrate and between the source/drain regions, the gate structure including a gate dielectric material around each of the nanosheets, a work function material around the gate dielectric material, a first capping material around the work function material, a second capping material around the first capping material, wherein the second capping material is thicker at a first location between the nanosheets than at a second location along a sidewall of the nanosheets, and a gate fill material over the second capping material.