Nano-FET Gate Stack Fluorination for Threshold Voltage Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in maintaining device performance and integration density, particularly in the formation of gate stacks and dielectric layers, which affect the flatband voltage and threshold voltage of transistors.
Innovation Solution
The implementation of a fluorine-treated gate dielectric layer followed by the deposition of a work function metal layer, where the fluorine treatment enhances the interface between the gate dielectric and the work function metal, increasing the flatband voltage and decreasing the threshold voltage, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to improve integration density, then more components can be integrated into a given area, but device performance deteriorates
Solution Approach 1:
The patent applies different materials and treatments to different regions of the gate stack. Specifically, a fluorine-containing dielectric layer is formed only in the gate stack region, while other regions receive different treatments. This localized approach allows optimization of electrical properties (flatband voltage, threshold voltage) in the active device region without affecting other areas, thereby maintaining device performance despite reduced feature sizes
Solution Approach 2:
The patent changes the chemical and physical parameters of the gate dielectric layer by introducing fluorine atoms through chemical vapor deposition. This alters the dielectric properties, work function, and interface characteristics of the gate stack, enabling control over flatband and threshold voltages. These parameter changes allow the device to maintain proper electrical characteristics even as overall dimensions are reduced to improve integration density
2Ease of manufacture
If conventional gate stack formation is used, then manufacturing process is simple, but flatband voltage and threshold voltage control is insufficient
Solution Approach 1:
The fluorine-containing dielectric layer is formed preliminarily during the gate stack formation process, before subsequent metal layer depositions. This preliminary fluorination treatment prepares the dielectric interface with optimal electrical properties, ensuring proper flatband and threshold voltage characteristics are established early in the process. This approach integrates voltage control into the base formation steps rather than requiring separate adjustment steps later
Solution Approach 2:
The gate dielectric stack comprises composite materials including silicon oxide, silicon nitride, and fluorine-containing dielectric layers. This composite structure combines the benefits of each material: silicon oxide provides good interface quality, silicon nitride provides high dielectric constant and stress control, and the fluorine-containing layer provides work function modulation and flatband voltage control. The composite approach achieves precise voltage control while maintaining compatibility with existing manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach leads to improved device performance by increasing the flatband voltage towards the band edge of the metal work function layer, reducing the threshold voltage, and enhancing overall transistor performance.
Implementation Method 1
The implementation of a fluorine-treated gate dielectric layer followed by the deposition of a work function metal layer, where the fluorine treatment enhances the interface between the gate dielectric and the work function metal
Implementation Method 2
the deposition of a work function metal layer
Data Source
AI summary
Embodiments include a device and method of forming a device, such as a nano-FET transistor, including a first nanostructure. A gate dielectric is formed around the first nanostructure. A gate electrode is formed over the gate dielectric, and the gate electrode includes a first work function metal. In the gate electrode, a first metal residue is formed at an interface between the gate dielectric and the first work function metal as a result of a treatment process performed prior to forming the first work function metal. The first metal residue has a metal element that is different than a metal element of the first work function metal.