Nano-FET Gate Stack Structure for Fluorine-Stable Threshold Voltage
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, issues arise from uneven fluorine distribution in the work function metal layers of transistor gate stacks, leading to instability in threshold voltage (Vt) and reduced performance in nano-FETs.
Innovation Solution
Incorporating a barrier layer between the fill metal and underlying work function metal layers during deposition to prevent fluorine diffusion, using fluorine-free precursors, thereby maintaining uniform fluorine distribution and improving Vt stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but uneven fluorine distribution in work function metal layers occurs leading to threshold voltage instability
Solution Approach 1:
A barrier layer is introduced as an intermediary between the fill metal and the work function metal layers. This barrier layer prevents fluorine diffusion from the fill metal into the work function metal, thereby maintaining uniform fluorine distribution and ensuring threshold voltage stability even as feature sizes are reduced to improve integration density.
2Area of stationary object
If feature size is reduced to improve integration density, then manufacturing area is optimized, but fluorine diffusion becomes more problematic causing performance degradation
Solution Approach 1:
The barrier layer serves as a mediator that blocks fluorine diffusion pathways. By placing this intermediate layer between the fill metal and work function metal, the harmful fluorine diffusion is prevented while maintaining the reduced feature size geometry needed for high integration density.
3Ease of manufacture
If conventional deposition is used to fill gate structures, then manufacturing process is simple, but fluorine contamination occurs in work function metal layers
Solution Approach 1:
The gate structure is segmented into distinct layers with the barrier layer positioned between the fill metal and work function metal. This segmentation allows the fill metal to be deposited using conventional simple processes while the barrier layer prevents fluorine contamination of the work function metal, thereby maintaining both manufacturing simplicity and fluorine distribution uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances Vt stability and control in nano-FETs by preventing uneven fluorine distribution, ensuring consistent performance and reliability in smaller feature sizes.
Implementation Method 1
Incorporating a barrier layer between the fill metal and underlying work function metal layers during deposition to prevent fluorine diffusion
Implementation Method 2
semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material
Data Source
AI summary
A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nanostructure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.