Nano-FET Gate Formation for Dense Nanowire Integration
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in maintaining integration density and improving performance while managing the complexities of nanostructure fabrication and gate dielectric formation.
Innovation Solution
The use of nanostructure field-effect transistors (nano-FETs) with gate-last and gate-first processes, involving the formation of nanostructures over fins on a substrate, and the deposition of gate dielectric layers and electrodes to create channel regions for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but fabrication complexity and process control difficulty increase
Solution Approach 1:
The fabrication process is divided into distinct stages: forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selective removal. This segmentation allows each step to be optimized independently, managing the overall fabrication complexity while achieving high integration density through systematic miniaturization
Solution Approach 2:
Mandrels are formed first as preliminary structures that guide the subsequent formation of spacers and nanostructures. The mandrels are removed after serving their guiding purpose, leaving behind precisely formed nanostructures. This preliminary action enables controlled feature formation at reduced dimensions without directly patterning the final structures
2Quantity of substance
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but manufacturing precision requirements become more stringent
Solution Approach 1:
Spacer materials serve as intermediaries that transfer the pattern from mandrels to final nanostructures. The conformal deposition of spacers ensures uniform thickness and precise dimensional control, while the selective removal process allows precise definition of final feature locations and sizes, maintaining manufacturing precision at reduced feature dimensions
Solution Approach 2:
The patent replaces direct lithographic patterning with a self-aligned spacer formation process. Instead of relying on lithography resolution to define final feature sizes, the process uses conformal film deposition and anisotropic etching to mechanically define dimensions, achieving better precision at smaller feature sizes
3Reliability
If gate dielectric layers are deposited over nanostructures to improve device performance, then electrical performance is enhanced, but process complexity increases
Solution Approach 1:
The gate structure formation is made dynamic through the gate-last approach, where the gate electrode is deposited after nanostructure formation, allowing the gate dimensions to be adjusted independently. The gate dielectric is deposited conformally and then planarized, enabling flexible optimization of gate thickness and dimensions to enhance electrical performance while managing process complexity through adaptive control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-performance nano-FETs with enhanced integration density, improved electrical performance, and reduced defects such as voids and seams in the gate electrode filling process.
Implementation Method 1
oxidizing a portion of the spacer sidewall with a plasma precursor
Implementation Method 2
plasma precursor
Data Source
AI summary
Semiconductor devices and methods of manufacture are presented. In embodiments a method of manufacturing the semiconductor device includes forming a fin from a plurality of semiconductor materials, depositing a dummy gate over the fin, depositing a plurality of spacers adjacent to the dummy gate, removing the dummy gate to form an opening adjacent to the plurality of spacers, widening the opening adjacent to a top surface of the plurality of spacers, after the widening, removing one of the plurality of semiconductor materials to form nanowires, and depositing a gate electrode around the nanowires.