Nano-FET Gate Structure With Fluorine-Treated Dielectric Interface
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in maintaining device performance and reliability, particularly in the formation of gate structures in transistors.
Innovation Solution
The implementation of a fluorine-treated gate dielectric layer followed by a work function metal (WFM) layer deposition, which enhances the interface properties and improves the flatband voltage and threshold voltage of transistors, leading to improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but device performance and reliability deteriorate
Solution Approach 1:
The patent applies parameter changes by treating the gate dielectric layer with fluorine, which modifies the chemical composition and electrical properties of the dielectric material. This treatment adjusts key parameters such as flatband voltage and threshold voltage to maintain device performance at scaled dimensions. The fluorine treatment creates specific interface properties that compensate for performance degradation caused by feature size reduction.
Solution Approach 2:
The invention implements local quality by applying fluorine treatment specifically at the interface between the gate dielectric and work function metal layer, rather than uniformly throughout the entire structure. This localized modification optimizes the critical interface region where electrical performance is most sensitive, while leaving other regions unchanged. The approach targets the specific location where performance degradation occurs due to scaling.
2Ease of manufacture
If conventional gate structure formation is used at scaled dimensions, then manufacturing simplicity is maintained, but flatband voltage and threshold voltage performance deteriorate
Solution Approach 1:
The patent employs preliminary action by performing fluorine treatment on the gate dielectric layer before depositing the work function metal layer. This pre-treatment prepares the dielectric surface with optimal interface properties, ensuring that subsequent metal deposition results in the desired flatband voltage and threshold voltage characteristics. The preliminary fluorine treatment prevents performance issues rather than correcting them after fabrication.
3Area of stationary object
If feature sizes are reduced for higher integration, then area utilization improves, but interface properties and voltage control worsen
Solution Approach 1:
The fluorine treatment modifies the electrical parameters of the gate dielectric interface, specifically adjusting flatband voltage and threshold voltage to maintain precise voltage control despite reduced feature sizes. The treatment changes the chemical and electrical characteristics of the dielectric material at the critical interface region, compensating for scaling effects.
Solution Approach 2:
The invention applies local quality by concentrating the fluorine treatment at the gate dielectric interface, the specific location where voltage control is most critical. This localized modification ensures that the scaled device maintains proper electrical characteristics without requiring changes to the overall device geometry or other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the flatband voltage towards the band edge of the WFM layer, decreases the threshold voltage, and enhances the overall performance of the resulting transistors.
Implementation Method 1
The implementation of a fluorine-treated gate dielectric layer followed by a work function metal (WFM) layer deposition, which enhances the interface properties and improves the flatband voltage and threshold voltage of transistors
Implementation Method 2
followed by a work function metal (WFM) layer deposition
Data Source
AI summary
Embodiments include a device and method of forming a device, such as a nano-FET transistor, including a first nanostructure. A gate dielectric is formed around the first nanostructure. A gate electrode is formed over the gate dielectric, and the gate electrode includes a first work function metal. In the gate electrode, a first metal residue is formed at an interface between the gate dielectric and the first work function metal as a result of a treatment process performed prior to forming the first work function metal. The first metal residue has a metal element that is different than a metal element of the first work function metal.