Nano-FET Memory Cell Layout With Under-Channel Horizontal Capacitor
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing integration density and read reliability while maintaining device performance, as conventional methods struggle to efficiently utilize space for capacitors within memory cells.
Innovation Solution
Incorporating a nano-FET and a horizontal capacitor that extends partially under the nano-FET, forming a memory cell with a coplanar top surface, allowing for increased capacitor volume without increasing area, using conventional CMOS processes for easy integration and reduced cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capacitor configurations are used in memory cells, then the device area is reduced, but the capacitor volume and read reliability are limited
Solution Approach 1:
The capacitor is configured in a horizontal orientation extending beneath the nano-FET channel, utilizing the vertical dimension and lateral space under the transistor structure. This three-dimensional integration allows the capacitor volume to be increased without proportionally increasing the overall memory cell footprint, as the capacitor shares the vertical space with the nano-FET structure above it
2Volume of stationary object
If capacitor volume is increased to improve read reliability, then the storage capacity is enhanced, but the device area increases
Solution Approach 1:
The horizontal capacitor is nested beneath the nano-FET structure, with the capacitor extending laterally under the channel region. The capacitor electrodes and dielectric layers are positioned in the space occupied by the substrate and lower dielectric layers, effectively nesting the capacitor within the vertical profile of the memory cell without requiring additional lateral area
Solution Approach 2:
The capacitor is configured in a horizontal orientation extending beneath the nano-FET channel, utilizing the vertical dimension and lateral space under the transistor structure. This three-dimensional integration allows the capacitor volume to be increased without proportionally increasing the overall memory cell footprint, as the capacitor shares the vertical space with the nano-FET structure above it
3Productivity
If integration density is increased by reducing feature size, then more components fit in a given area, but manufacturing complexity increases
Solution Approach 1:
The memory cell is segmented into distinct functional regions: the nano-FET with gate, channel, and source/drain regions, and the separate horizontal capacitor structure with first and second electrodes and dielectric layers. This segmentation allows each component to be optimized independently while maintaining compatibility with standard CMOS fabrication processes
Solution Approach 2:
The horizontal capacitor structure serves multiple functions: it provides the storage node for data retention, acts as a reference for read operations, and is integrated with the nano-FET to form a complete memory cell. The configuration is compatible with existing CMOS processes, making it universally applicable to standard semiconductor manufacturing
Data Source
AI summary
An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.