Nano-FET Inner Spacer Formation With Reduced Seam Defects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in the fabrication process that affect the integrity and functionality of nanostructures, leading to manufacturing defects and reduced performance.
Innovation Solution
A method is employed to form a stack of semiconductor layers over a substrate, patterning them into nanostructures with inner spacers that are seam-free or have reduced seams, followed by epitaxially growing source/drain regions and replacing sacrificial material with a gate structure, enhancing the reliability and performance of nano-FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing defects and reduced performance occur
Solution Approach 1:
The patent applies segmentation by forming inner spacers as separate, distinct structures within the nano-FET fabrication process. Multiple inner spacer layers are deposited and patterned in sequence, creating segmented isolation regions that prevent manufacturing defects while enabling continued scaling. This segmentation allows the fabrication process to maintain precision even as minimum feature sizes are reduced for higher integration density.
Solution Approach 2:
The patent employs preliminary action by forming inner spacers before final gate structure fabrication. This advance preparation creates protective isolation structures that prevent defects during subsequent manufacturing steps. The inner spacers are formed in advance to establish a foundation that maintains nanostructure integrity throughout the remaining fabrication process, even as feature sizes continue to shrink.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing defects occur
Solution Approach 1:
The inner spacer structure segments the fabrication process into controlled stages, with each inner spacer layer providing isolation and protection. This segmentation prevents defect propagation and maintains device reliability even as integration density increases through continued feature size reduction. The multi-layer inner spacer approach creates redundant protection against manufacturing variations.
Solution Approach 2:
The patent implements beforehand cushioning by creating inner spacers that act as protective buffers during fabrication. These pre-formed structures cushion against potential manufacturing defects by providing isolation and structural support before critical subsequent steps occur. This protective measure ensures device reliability is maintained even when scaling to smaller feature sizes for higher integration density.
3Ease of manufacture
If inner spacers are formed with seams, then fabrication process is simpler, but manufacturing defects and reduced yield occur
Solution Approach 1:
The patent segments the inner spacer formation into multiple discrete layers rather than attempting to form a single seamless structure. This segmentation into first and second inner spacer layers, each deposited and patterned separately, actually simplifies the fabrication process by breaking down a complex seamless formation challenge into manageable, repeatable steps while maintaining or improving overall integrity.
Solution Approach 2:
The patent applies partial action by forming inner spacers in multiple sequential steps rather than attempting complete seamless formation in one step. Each inner spacer layer is formed to a specific thickness and pattern, with the cumulative effect providing the necessary isolation and structural support. This partial, incremental approach improves manufacturing precision while keeping the overall process manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described method improves the yield and functionality of nano-FETs by reducing manufacturing defects and enhancing performance through improved integrity of inner spacers and gate structures.
Implementation Method 1
etching a first sidewall of the first nanostructure to be recessed from a second sidewall of the second nanostructure
Implementation Method 2
depositing a first dielectric layer along the first sidewall, the second sidewall, and the substrate
Implementation Method 3
epitaxially growing source/drain regions
Data Source
AI summary
In an embodiment, a method includes forming a first nanostructure and a second nanostructure over a substrate, the first nanostructure being interposed between the substrate and the second nanostructure; etching a first sidewall of the first nanostructure to be recessed from a second sidewall of the second nanostructure; depositing a first dielectric layer along the first sidewall, the second sidewall, and the substrate; etching a recess in the first dielectric layer, the recess extending toward the first sidewall of the first nanostructure; depositing a second dielectric layer in the recess over the first dielectric layer; and removing the first dielectric layer and the second dielectric layer from the second sidewall and the substrate.