Memory cell and method
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to increase integration density and improve read reliability of memory cells while maintaining device performance and reducing costs.
Innovation Solution
The integration of a nano-FET and a horizontal capacitor in a memory cell, where the capacitor extends partially under the nano-FET, allowing for increased capacitor volume without increasing the memory cell area, achieved through conventional CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitor volume is increased to improve read reliability, then the memory cell area increases
Solution Approach 1:
The capacitor is repositioned from a planar configuration to a three-dimensional configuration that extends underneath the transistor structure. This vertical integration allows the capacitor volume to increase without proportionally increasing the lateral memory cell footprint, effectively utilizing the third dimension (depth) to resolve the area constraint.
Solution Approach 2:
The capacitor structure is nested underneath the transistor, with the capacitor extending into the space below the transistor gate and source/drain regions. This nesting arrangement allows both components to share the same lateral footprint while maintaining sufficient separation for electrical isolation, thereby increasing capacitor volume without increasing overall cell area.
2Productivity
If the integration density is increased by reducing minimum feature size, then the manufacturing precision requirements increase
Solution Approach 1:
The memory cell is segmented into distinct functional regions with the capacitor and transistor formed as separate structures. This segmentation allows each component to be optimized independently and formed using standard CMOS process steps, reducing the cumulative precision requirements compared to more integrated approaches.
Solution Approach 2:
The invention utilizes conventional CMOS fabrication processes to form both the transistor and capacitor structures, making the manufacturing approach universal and compatible with existing semiconductor manufacturing infrastructure. This avoids the need for specialized process steps that would demand higher precision control.
Data Source
AI summary
An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.