Nano-FET Gate Stack Using Oxide Interposer to Block Ge Diffusion
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Solution Overview
Problem
As semiconductor devices strive for increased integration density, managing and improving the performance of densely packed structures becomes complex, particularly due to issues like germanium diffusion and NMG extrusion defects in nano-FETs, which affect electrical characteristics and channel resistance.
Innovation Solution
The use of a Disposable Oxide Interposer (DOI) process replaces silicon germanium with oxide materials like silicon dioxide or silicon oxynitride as dummy material in transistor manufacturing, reducing germanium diffusion and enhancing the performance of nano-FETs by increasing silicon channel height and reducing channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon germanium is used as dummy material in transistor manufacturing, then the manufacturing process is simplified, but germanium diffusion occurs causing NMG extrusion defects and increased channel resistance
Solution Approach 1:
The patent employs a disposable oxide interposer layer that is intentionally designed to be removed after serving its protective function during manufacturing. This disposable approach allows the use of oxide materials that prevent germanium diffusion without requiring permanent retention, resolving the contradiction between manufacturing ease and device reliability by using a temporary sacrificial structure.
Solution Approach 2:
The oxide interposer acts as an intermediary material between the silicon germanium source/drain regions and the channel. This intermediate layer prevents direct interaction causing germanium diffusion, while being removable afterward. The mediator approach enables simplified manufacturing with silicon germanium while eliminating the harmful diffusion effect through the temporary protective barrier.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but additional manufacturing problems and defects arise
Solution Approach 1:
The patent changes the material parameter of the dummy interposer from silicon germanium to oxide material, which fundamentally alters the diffusion characteristics. This parameter change enables reduced minimum feature size by preventing germanium diffusion that would otherwise become problematic at smaller dimensions, thereby supporting higher integration density while maintaining manufacturing precision.
3Reliability
If germanium diffusion is prevented using oxide interposer, then channel resistance is reduced and drive current increases, but additional process steps are required
Solution Approach 1:
The oxide interposer is formed in advance before source/drain region formation, preliminarily establishing the protective barrier against germanium diffusion. This preliminary action prevents the need for complex post-processing steps to correct diffusion defects, as the protection is proactively in place during the critical manufacturing stages, thereby reducing overall process complexity despite the additional initial step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in nano-FETs with lower resistance and higher drive currents, improving the overall performance of semiconductor devices by minimizing defects and enhancing electrical characteristics.
Implementation Method 1
replaces silicon germanium with oxide materials like silicon dioxide or silicon oxynitride as dummy material in transistor manufacturing, reducing germanium diffusion
Data Source
AI summary
In an embodiment, a method of manufacturing a semiconductor device includes forming a multi-layer stack over a substrate, the multi-layer stack comprising alternating layers of first semiconductor layers and second semiconductor layers, forming a first PMOS pull down transistor, the forming the first PMOS pull down transistor including removing the first semiconductor layers in a first region of the substrate, forming a disposable material between the second semiconductor layers in the first region, forming source/drain regions adjacent the second semiconductor layers and the disposable material in the first region, and replacing the disposable material in the first region with a first metal gate structure, and forming a first NMOS pull up transistor, the forming the first NMOS pull up transistor comprising replacing the first semiconductor layers in a second region of the substrate with a second metal gate structure.