Nano-FET Gate Stack Sequencing for Work Function Isolation
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in maintaining the integration density and performance of transistors, particularly in preventing work function tuning layers from degrading p-type devices during the manufacturing process of nano-FETs.
Innovation Solution
The method involves forming work function tuning layers for n-type devices before p-type devices, using sacrificial layers to prevent contamination, and applying a protection layer to inhibit diffusion, allowing for more accurate tuning of threshold voltages and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If work function tuning layers are formed for both n-type and p-type devices using the same process, then manufacturing simplicity is maintained, but the p-type devices degrade due to contamination from the n-type work function tuning layer
Solution Approach 1:
The patent segments the work function tuning process by separating n-type and p-type device processing into distinct stages. The n-type work function tuning layer is formed first, then removed from p-type regions before forming the p-type work function tuning layer. This segmentation prevents contamination while maintaining manufacturing feasibility through structured process separation.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary elements that temporarily occupy spaces during processing. These sacrificial layers prevent the n-type work function tuning layer from contaminating p-type regions, and are subsequently removed. The intermediary sacrificial layers enable precise control over where each work function tuning layer is formed without direct physical separation of the processes.
2Reliability
If work function tuning layers are formed sequentially with protective measures, then device integrity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming sacrificial layers and n-type work function tuning layers in advance, before the p-type processing begins. This preliminary structuring establishes protective barriers and defined regions that simplify subsequent steps, reducing the need for complex real-time adjustments during p-type work function tuning layer formation.
Solution Approach 2:
The patent employs discarding and recovering by removing sacrificial layers and portions of the n-type work function tuning layer after they have served their protective function. These discarded elements enabled precise control during manufacturing, and their removal recovers the final clean structure needed for device operation, balancing protection needs with final device simplicity.
3Productivity
If feature sizes are reduced to increase integration density, then more components fit in a given area, but maintaining threshold voltage precision becomes more difficult
Solution Approach 1:
The patent applies local quality by forming different work function tuning layers with specific materials and thicknesses tailored to each device type (n-type vs. p-type) and specific region. This localized customization of layer properties enables precise threshold voltage control for each device type even as overall feature sizes shrink, maintaining manufacturing precision through region-specific optimization rather than uniform processing.
Data Source
AI summary
An embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region, a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region, a gate dielectric layer wrapping around each of the first and second sets of nanostructures, a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures, a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, and a fill layer on the second work function tuning layer.