Nano-scale Electrical Contacts via Liner Segmentation
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Solution Overview
Problem
Emerging memory technologies, such as PCM and RRAM, require high electrical current densities, leading to large memory cell access devices that are inefficient and costly, as conventional photolithography limits the formation of small, effective electrical contacts.
Innovation Solution
The method involves forming nano-scale pores and electrical contacts by depositing dielectric and sacrificial liners with precise thicknesses, allowing for the reduction of electrical contact size and current requirements, enabling smaller access devices and improved current density management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used to form electrical contacts, then the manufacturing process is simple and well-established, but the electrical contact size is limited to larger dimensions (about 22 nm by photolithography) which increases current requirements
Solution Approach 1:
The fabrication process is segmented into multiple sequential steps: forming first liners, forming second liners, selectively removing second liners to create trenches, and filling with conductive material. This segmentation enables precise control of electrical contact dimensions (7.5 nm by 22 nm) that cannot be achieved through conventional single-step photolithography
Solution Approach 2:
Liners are formed in advance with precisely controlled thicknesses before the final electrical contact formation. The first liner (7.5 nm thick) and second liner are deposited beforehand, establishing the dimensional template for the eventual electrical contact, which enables sub-photolithography precision
2Power
If larger electrical contacts are formed to handle high current densities, then the current carrying capacity is sufficient, but the access device size increases leading to reduced device efficiency and increased cost
Solution Approach 1:
The electrical contact cross-sectional area is reduced from conventional dimensions (22 nm × 22 nm = 484 nm²) to a smaller dimension (7.5 nm × 22 nm = 165 nm²) through precise liner thickness control. This parameter change maintains sufficient current carrying capacity while reducing access device size and improving overall device efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of smaller, more uniform nano-scale electrical contacts, reducing power consumption and improving controllability, allowing for efficient operation of emerging memory technologies with lower current demands.
Implementation Method 1
depositing dielectric and sacrificial liners with precise thicknesses
Data Source
AI summary
Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.