Nano-Sheet Transistor Isolation via Trench Segmentation
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Solution Overview
Problem
Conventional methods for producing nano-sheet transistor devices on bulk semiconductor substrates face challenges such as parasitic planar transistors causing leakage and capacitance issues, which are difficult to isolate effectively, leading to inefficiencies in high drive currents and power consumption.
Innovation Solution
The method involves forming a sacrificial gate and stack of materials above a semiconductor substrate, creating trenches in source/drain areas, depositing a conformal layer of isolation material, and performing recess etching to define a recessed upper surface, thereby isolating the nano-sheet device from the substrate and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nano-sheet devices are made on a bulk semiconductor substrate, then device integration is achieved, but parasitic planar transistors cause leakage and capacitance issues
Solution Approach 1:
The substrate is segmented into isolated regions by forming trenches that divide the bulk semiconductor substrate into separate islands, each supporting an individual nano-sheet device. This segmentation prevents parasitic planar transistor formation between adjacent devices while maintaining high device integration density.
Solution Approach 2:
The harmful parasitic planar transistor regions are extracted by removing substrate material through trench formation. The trenches physically remove the continuous substrate that would otherwise form parasitic conduction paths, isolating each nano-sheet device's source and drain regions.
2Object-generated harmful factors
If isolation material is formed between gate structure and substrate, then parasitic capacitance is reduced, but processing complexity increases
Solution Approach 1:
The trenches are formed preliminarily before depositing the isolation material, creating pre-defined isolation regions that guide subsequent material deposition. This preliminary trench formation simplifies the overall process by establishing clear boundaries for isolation material placement, reducing the need for complex masking and patterning steps.
Solution Approach 2:
The trench structure serves as an intermediary form that facilitates the deposition of isolation material. By creating these intermediate trench structures, the process enables straightforward conformal deposition of isolation material that automatically fills the trenches and provides effective electrical isolation without requiring additional complex processing.
3Object-generated harmful factors
If trenches are formed and isolation material deposited, then device isolation is achieved, but manufacturing time increases
Solution Approach 1:
The trench formation and isolation material deposition are merged into a coordinated process sequence where trenches are formed and immediately filled with isolation material in a continuous manufacturing flow. This merging of operations eliminates intermediate handling steps and reduces overall manufacturing time while achieving complete device isolation.
Solution Approach 2:
The process rushes through the isolation formation by using direct trench filling methods that quickly establish isolation regions without prolonged intermediate steps. The conformal deposition and filling operations are performed rapidly to minimize the time devices spend in processing while ensuring complete isolation is achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively isolates the nano-sheet transistor device, reducing leakage and capacitance, enabling higher drive currents with low power consumption, and simplifying the manufacturing process while maintaining product yield.
Implementation Method 1
a conformal deposition process is performed so as to deposit a conformal layer of isolation material on the sacrificial gate and on the substrate
Implementation Method 2
a recess etching process is performed to remove portions of the conformal layer of isolation material, thereby defining a recessed upper surface
Data Source
AI summary
A method includes forming a sacrificial gate and a stack of materials above a semiconductor substrate, forming a trench in each of the source/drain areas of the device, wherein each trench extends into the semiconductor substrate, forming an empty space under the sacrificial gate structure, the empty space being vertically positioned between the stack of materials and the semiconductor substrate, wherein the empty space is in communication with the trenches, performing a conformal deposition process so as to deposit a conformal layer of a device isolation material adjacent at least the sacrificial gate while at least partially filling the empty space and substantially filling the trenches, and performing a recess etching process to remove at least portions of the conformal layer positioned adjacent the sacrificial gate, thereby defining a recessed upper surface of the device isolation material.