Nanochannel FET Single Diffusion Break via Self-Aligned Low-k Spacer
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Solution Overview
Problem
Current methods for forming single diffusion breaks in nanowire and nanosheet semiconductor devices face challenges due to inconsistent strain and morphology issues, leading to parasitic current and capacitance problems, and require precise alignment and complex etching processes.
Innovation Solution
The method involves allowing nanowires or nanosheets to run continuously through the diffusion break area, converting the replacement gate into a local 'cut gate' by removing polysilicon, and filling the dummy gate with a dielectric, ensuring consistent epitaxial growth and reducing parasitic issues by self-aligning the FIN break to the low-k spacer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form single diffusion breaks in nanowire and nanosheet devices, then diffusion break functionality is achieved, but inconsistent strain and morphology issues occur leading to parasitic current and capacitance problems
Solution Approach 1:
The low-k spacer automatically positions the FIN break through self-alignment during the deposition process, eliminating the need for separate alignment steps. The spacer material itself serves as the alignment reference, ensuring consistent positioning without additional complexity
Solution Approach 2:
The low-k spacer is deposited beforehand to establish the alignment reference before the FIN break is formed. This preliminary structure enables subsequent self-aligned processing steps to occur without requiring precise manual alignment
2Manufacturing precision
If precise alignment and complex etching processes are used to form single diffusion breaks, then diffusion break functionality is achieved, but process complexity increases
Solution Approach 1:
The structure self-aligns through the physical presence of the low-k spacer, which automatically defines the break position. This eliminates the need for complex alignment procedures and reduces process steps while maintaining high precision
Solution Approach 2:
The complex alignment and positioning steps are removed from the process by using self-alignment. Only the essential etching step remains, significantly simplifying the overall process while maintaining manufacturing precision
3Ease of manufacture
If nanowires or nanosheets are cut to form diffusion breaks, then diffusion break functionality is achieved, but strain consistency and morphology uniformity deteriorate
Solution Approach 1:
The low-k spacer acts as an intermediary structure that defines the break position without requiring physical cutting of the nanowire/nanosheet. The spacer mediates the formation process, allowing the channel to remain continuous while still creating the diffusion break functionality
Solution Approach 2:
The low-k spacer is formed in advance to establish where the diffusion break should occur. This preliminary structure guides subsequent processing steps and ensures that when the break is formed, the nanowire/nanosheet morphology remains consistent with proper strain distribution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves consistent S/D epitaxial growth across all regions, minimizes strain, and reduces parasitic and capacitance-related issues, while simplifying the process by eliminating the need for precise alignment and complex etching.
Implementation Method 1
self-aligning the FIN break to the low-k spacer
Implementation Method 2
filling the dummy gate with a dielectric
Implementation Method 3
ensuring consistent epitaxial growth
Data Source
AI summary
A method of forming a semiconductor device includes providing a starting structure including a substrate having thereon a plurality of gate regions alternately arranged with a plurality of source/drain (S/D) regions, wherein each of the gate regions includes a nanochannel structure having an intermediate portion surrounded by a replacement gate, and opposing end portions surrounded by respective gate spacers such that the nanochannel structure extends through the replacement gate and the gate spacers of the gate region. Each of the S/D regions includes an S/D structure extending through the S/D region to connect nanochannel structures of first and second adjacent gate regions provided on opposing sides of the S/D region respectively. The first adjacent gate region is converted into a single diffusion break including a dummy gate structure, and the second adjacent gate region is converted into an active gate including an active gate structure configured to create a current channel within the nanochannel structure of the second adjacent gate region.