Nonvolatile Memory Nanocluster Isolation for Data Reliability
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Solution Overview
Problem
Existing semiconductor memory devices using silicon nanoclusters for two-bit data storage face issues with lateral charge transport, increased manufacturing costs due to additional masking steps, larger device size, and voltage limitations caused by thin gate dielectrics, leading to unreliable data storage and potential damage during erase operations.
Innovation Solution
A method for forming a multiple-bit nonvolatile memory device involves a semiconductor substrate with a nitrided oxide layer, a polysilicon gate layer, and selectively deposited silicon nanoclusters on either side of the gate, with undercut regions and sidewall spacers to create physically isolated charge storage regions, reducing bit disturb and allowing for variable gate oxide thickness and voltage application without additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single continuous layer of silicon nanoclusters is used to store two bits, then the device structure is simpler, but lateral charge transport occurs resulting in disturbed data bits and unreliable data storage
Solution Approach 1:
The patent divides the nanocluster layer into two separate discontinuous layers: a first nanocluster layer for storing a first bit and a second nanocluster layer for storing a second bit. This segmentation prevents lateral charge transport between bits by physically isolating the charge storage regions, thereby maintaining data reliability while still achieving two-bit storage capability.
2Reliability
If nanoclusters are removed from the center of the memory device to avoid lateral charge transport, then data storage reliability improves, but additional masking steps are required increasing manufacturing cost
Solution Approach 1:
The patent forms the first and second nanocluster layers at different stages of the fabrication process. The first nanocluster layer is formed before the gate structure, and the second nanocluster layer is formed after gate patterning. This preliminary and sequential formation eliminates the need for additional masking steps to remove center nanoclusters, as the nanoclusters are selectively present only where needed from the outset.
3Reliability
If nanoclusters are separated into source and drain regions, then lateral charge transport is avoided, but the device size increases
Solution Approach 1:
The patent utilizes vertical stacking to separate the first and second nanocluster layers in the thickness direction rather than only lateral separation. The first nanocluster layer is positioned at a first thickness and the second nanocluster layer at a second thickness, allowing compact in-plane arrangement while maintaining vertical isolation. This dimensional approach reduces the overall device footprint compared to purely lateral separation.
4Productivity
If thin gate dielectric is used in the center of the memory device, then device integration is improved, but high erase voltages damage or rupture the gate dielectric
Solution Approach 1:
The patent implements variable gate dielectric thickness with different regions having different thicknesses. The gate dielectric is thinner in regions where high voltage is not applied and thicker in regions where high erase voltages are applied. This local quality variation allows the device to achieve good integration in most areas while maintaining gate dielectric integrity in high-voltage regions, resolving the contradiction between integration and dielectric strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes manufacturing complexity, enhances data reliability by isolating bits, and accommodates a range of program and erase voltages, improving the overall performance and durability of the memory device.
Implementation Method 1
a nitrided oxide layer over the semiconductor substrate
Implementation Method 2
silicon nanoclusters on either side of the gate
Data Source
AI summary
In making a multi-bit memory cell, a first insulating layer is formed over a semiconductor substrate. A second insulating layer is formed over the first insulating layer. A layer of gate material is formed over the second insulating layer and patterned to leave a gate portion. The second insulating layer is etched to undercut the gate portion and leave a portion of the second insulating layer between the first insulating layer and the gate portion. Nanocrystals are formed on the first insulating layer. A first portion of the nanocrystals is under the gate portion on a first side of the portion of the second insulating layer and a second portion of the nanocrystals is under the gate portion on a second side of the portion of the second insulating layer. The first and second portions of the nanocrystals are for storing logic states of first and second bits, respectively.