NAND Memory Cells with Nanocluster Charge Trapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flash memory technologies face challenges in achieving large memory windows, good charge retention, and uniformity across NAND arrays due to parasitic capacitive coupling and stress-induced gate leakage, particularly when transitioning to multilevel cell (MLC) devices.
Innovation Solution
The formation of memory cells with charge-trapping nanoclusters over a tunnel dielectric, accompanied by the deposition of electrically insulative material and a blocking dielectric, which enables the creation of multiple charge-trapping zones with varying charge-trapping centers, enhancing programming efficiency and memory states separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge-trapping materials are used in non-volatile memory cells, then charge retention is improved, but memory window size and charge retention uniformity deteriorate
Solution Approach 1:
The charge-trapping layer is segmented into multiple discrete nanoclusters distributed throughout the dielectric layer rather than using a continuous charge-trapping material. This segmentation allows for better control of charge distribution and reduces variability in memory window across devices while maintaining good charge retention properties.
Solution Approach 2:
Different regions of the memory cell structure have different dielectric materials with optimized properties for their specific functions. The tunnel dielectric, charge-trapping dielectric, and blocking dielectric are each tailored to provide local optimization for charge injection, charge trapping, and charge blocking respectively, improving overall device performance and uniformity.
2Loss of information
If floating gate is charged to store data, then memory states are achieved, but parasitic capacitive coupling and stress-induced gate leakage occur
Solution Approach 1:
The harmful parasitic capacitive coupling and stress-induced gate leakage effects are extracted and eliminated by replacing the traditional floating gate structure with a charge-trapping dielectric layer containing nanoclusters. This extraction removes the source of parasitic effects while preserving the essential charge storage function for data retention.
Solution Approach 2:
The charge-trapping dielectric layer with nanoclusters acts as an intermediary between the tunnel dielectric and blocking dielectric, providing a controlled mechanism for charge storage that eliminates direct parasitic coupling paths. This intermediary structure enables charge trapping without the harmful side effects of traditional floating gate designs.
3Quantity of substance
If multilevel cell (MLC) devices are used to increase density, then memory capacity is doubled, but memory states separation becomes difficult
Solution Approach 1:
The patent extends the charge-trapping structure into the vertical dimension by distributing nanoclusters throughout the thickness of the charge-trapping dielectric layer. This three-dimensional charge distribution provides additional control dimensions for creating distinct charge levels, enabling clear separation of multiple memory states while maintaining high storage density.
Solution Approach 2:
The patent controls multiple parameters including nanocluster size, concentration, spatial distribution, and dielectric layer thickness to optimize the charge trapping characteristics. By precisely controlling these parameters, distinct charge levels corresponding to different memory states can be clearly separated, enabling reliable MLC operation with improved state discrimination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves memory window size and charge retention, allowing for clearer separation of memory states in MLC devices, thereby addressing the challenges of parasitic capacitive coupling and stress-induced gate leakage, and achieving uniformity across the NAND array.
Implementation Method 1
deposition of charge-trapping nanoclusters over a tunnel dielectric
Implementation Method 2
deposition of electrically insulative material over and between the nanoclusters
Data Source
AI summary
Some embodiments include methods of forming memory cells. A semiconductor construction may be provided, with such construction including tunnel dielectric material over a semiconductor substrate. The construction may be placed within a chamber. While the construction is within the chamber, a plurality of charge-trapping centers may be dispersed over the tunnel dielectric material. The charge-trapping centers may be nanoclusters formed by sputter-depositing metallic nanoparticles into an aggregation chamber, and then aggregating groups of the nanoparticles into the nanoclusters. Also while the construction is within the chamber, electrically insulative material may be formed over and between the charge-trapping centers. Control gate material may then be formed over the electrically insulative material.