Nanocrystal Bitcell Process Integration for High Density Memory
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Solution Overview
Problem
Current EEPROM devices face challenges with high wordline and bitline sheet resistances, and the scalability of fabrication processes, especially at device sizes below 90 nm, due to reliance on spacer structures and high voltage requirements.
Innovation Solution
A fabrication process using photolithographic techniques to define control gates or floating gates, combined with silicidation of gate structures and implant regions, which reduces resistance and improves reproducibility and scalability, and the use of nanocrystal charge storage materials to enhance programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Fowler-Nordheim tunneling is used for programming, then programming can be achieved, but very high voltages are needed which compromise device reliability and process scalability
Solution Approach 1:
The patent changes the programming mechanism from Fowler-Nordheim tunneling requiring very high voltages to channel hot electron injection using moderate voltages (e.g., 5V). This parameter change in the programming method eliminates the need for high voltage generators while achieving reliable programming, directly resolving the contradiction between reliability and voltage requirements.
Solution Approach 2:
The patent substitutes the high-voltage Fowler-Nordheim tunneling mechanism with a moderate-voltage channel hot electron injection mechanism. This substitution replaces the need for complex high-voltage generation circuitry with simpler charge pumping circuits, improving device reliability and scalability while maintaining programming functionality.
2Quantity of substance
If device sizes are scaled down, then memory density increases, but the relative area of charge pumps and high-voltage switching circuitry increases with respect to useful memory area
Solution Approach 1:
The patent changes the voltage parameter from very high voltages (required for Fowler-Nordheim tunneling) to moderate voltages (5V for channel hot electron injection). This parameter change eliminates the need for large high-voltage switching circuitry and complex charge pumps, allowing memory density to increase without proportionally increasing circuitry area.
Solution Approach 2:
The patent extracts and eliminates the high-voltage generator and associated high-voltage switching circuitry from the memory device. By using channel hot electron injection with moderate voltages, these large circuit components are removed, increasing the useful memory area relative to total device area.
3Productivity
If channel hot electron injection is used, then programming can be achieved, but high power is needed which becomes difficult to generate on-chip as devices are scaled down
Solution Approach 1:
The patent changes the voltage parameter from very high voltages (Fowler-Nordheim) to moderate voltages (5V channel hot electron injection). This parameter change reduces power consumption while maintaining programming speed, making it feasible to generate required power on-chip even as devices are scaled down.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in highly reproducible and scalable nonvolatile memory devices with lower wordline and bitline sheet resistances, improved programming speed, and reduced current/voltage requirements, enabling the production of dense memory devices with enhanced performance.
Implementation Method 1
In a nonvolatile memory device, two bits of information are stored in each memory cell by storing electrical charge in nanocrystals in the bulk of the semiconductor substrate
Implementation Method 2
an implant region is formed in the substrate between the first and second sets of memory stacks, and a silicide layer is formed over the implant region
Data Source
AI summary
A method for making a multibit non-volatile memory cell structure is provided herein. In accordance with the method, a semiconductor substrate (101) is provided, and first and second sets of memory stacks (103, 105, 107, and 109) are formed on the substrate, each memory stack including a control gate (111) and a layer of memory material (113). A source/drain region (123) is then formed between the first and second sets of memory stacks, and a silicide layer (125) is formed over the source/drain region.