Nanocrystal Floating Gate Transistor Fabrication
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Solution Overview
Problem
Existing electrically programmable flash memories face constraints in space and power consumption, particularly in smart card applications, due to high programming voltages and low injection efficiency of hot-carrier-injection transistors, limiting the number of transistors that can be programmed simultaneously.
Innovation Solution
A process for fabricating transistors with a floating gate comprising electrically conductive nanoparticles, where part of the floating gate on the source side is deoxidized and oxidized to form an insulating layer, optimizing the distribution of nanoparticles near the drain and reducing their presence near the source, resulting in a more efficient vertical electric field and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hot carrier injection is used for programming flash memories, then electrical charge can be injected into the floating gate, but the injection efficiency is low and high programming current is required
Solution Approach 1:
The patent applies local quality by creating a non-uniform distribution of nanocrystals within the floating gate, with higher concentration near the drain region and lower concentration near the source region. This spatial variation in nanocrystal density optimizes the local electric field distribution, enhancing hot carrier injection efficiency specifically in the high-field region near the drain while reducing overall power consumption.
Solution Approach 2:
The patent changes the physical and chemical parameters of the floating gate by incorporating nanocrystals with specific size ranges (2-20 nm) and controlling their spatial distribution through selective oxidation processes. These parameter changes modify the electric field distribution and carrier transport properties, improving injection efficiency without requiring proportionally high programming currents.
2Reliability
If high programming voltages are applied to flash memories, then charge injection into the floating gate is achieved, but leakage currents increase and power consumption rises
Solution Approach 1:
By creating regions with different nanocrystal densities (higher near drain, lower near source), the patent optimizes the local electric field distribution. This allows effective charge injection in the high-field region while reducing field-induced leakage in other regions, thereby lowering overall power consumption and harmful leakage currents.
3Quantity of substance
If the number of simultaneously programmable transistors is increased, then memory capacity is improved, but power consumption constraints are exceeded
Solution Approach 1:
The patent modifies the floating gate structure by incorporating nanocrystals with optimized size and distribution parameters, which enhances charge retention efficiency. This allows for lower programming currents to be used, thereby enabling a greater number of transistors to be programmed simultaneously within the same power consumption budget.
4Area of stationary object
If flash memories are designed for small footprint, then space constraints are satisfied, but programming efficiency and power consumption become problematic
Solution Approach 1:
The patent achieves small footprint by optimizing the vertical structure with a thin floating gate containing spatially varying nanocrystal density. The non-uniform nanocrystal distribution enhances programming efficiency within the constrained volume, allowing effective charge injection without requiring excessive programming power, thus satisfying both space and power constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach allows for a transistor with reduced power consumption and a smaller footprint, enabling more efficient programming with lower power usage, suitable for high-density memory applications in smart cards and other semiconductor devices.
Implementation Method 1
deoxidizing part of the floating gate located on the source side
Implementation Method 2
oxidizing the space resulting from the prior deoxidation so as to form an insulating layer
Implementation Method 3
The deoxidizing step may comprise a wet etching method of the buffered oxide etch (BOE) type
Implementation Method 4
electrically conductive nanoparticles able to accumulate electrical charge
Data Source
AI summary
A process for fabricating a transistor may include forming source and drain regions in a substrate, and forming a floating gate having electrically conductive nanoparticles able to accumulate electrical charge. The process may include deoxidizing part of the floating gate located on the source side, and oxidizing the space resulting from the prior deoxidation so as to form an insulating layer on the source side.