Nanocrystal Memory Array Fabrication via Silicon Germanium Oxidation
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Solution Overview
Problem
Current non-volatile memory devices face challenges in achieving high integration density, low power consumption, and fast access speed while maintaining compactness and reliability, particularly in the physical configuration of memory cells where electron tunneling affects capacity.
Innovation Solution
The development of a nanocrystal floating gate non-volatile memory array using a crossbar configuration with silicon and silicon germanium layers, where germanium nanocrystals are formed and oxidized to create a tunnel oxide layer, allowing for self-alignment and higher density storage without the need for selector switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory cell configuration with floating gate and series transistors is used, then electron tunneling capability is achieved, but integration density is limited due to complex physical structure
Solution Approach 1:
The memory cell structure is segmented into distinct functional layers: charge storage layer (nanocrystals), tunnel oxide layer, blocking oxide layer, and semiconductor layer. This segmentation allows each layer to be optimized independently for its specific function while achieving higher integration density through vertical stacking rather than planar expansion.
Solution Approach 2:
The invention transitions from a planar two-dimensional memory cell layout to a vertical three-dimensional structure with multiple oxide layers stacked above the semiconductor layer. This dimensional change enables higher storage density by utilizing the vertical space above each transistor rather than requiring additional transistors in the plane.
2Quantity of substance
If higher integration density is achieved through reduced cell size, then storage capacity increases, but power consumption increases due to smaller tunneling distances and increased cell count
Solution Approach 1:
The oxide layers have different local qualities: the tunnel oxide layer (5-15 nm) has lower thickness to enable electron tunneling, while the blocking oxide layer (15-30 nm) has greater thickness to prevent electron leakage. This local differentiation allows the structure to achieve both high storage capacity and low power consumption by optimizing each region for its specific function.
Solution Approach 2:
The invention changes the thickness parameters of the oxide layers to achieve optimal performance: tunnel oxide thickness of 5-15 nm for sufficient tunneling current, and blocking oxide thickness of 15-30 nm for adequate charge retention. These parameter optimizations enable high-density storage while maintaining low power consumption through controlled electron tunneling.
3Speed
If access speed is increased through faster electron tunneling, then read/write operations improve, but reliability decreases due to potential charge leakage and instability
Solution Approach 1:
The blocking oxide layer acts as an intermediary between the charge storage layer and the environment, preventing charge leakage while allowing controlled tunneling during write operations. This intermediary structure maintains reliability by isolating the stored charge from degradation mechanisms while preserving fast access speed through the tunnel oxide layer.
Solution Approach 2:
The memory structure uses a composite of different oxide materials with distinct properties: tunnel oxide for electron transport, blocking oxide for charge isolation, and charge storage layer for data retention. This composite material approach enables simultaneous achievement of fast access speed through the tunnel oxide and high reliability through the blocking oxide and stable charge storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density flash storage with low power consumption and fast access speed, achieving approximately 10 Gb/mm² without the need for selector switches, while maintaining reliability and compactness.
Implementation Method 1
the silicon germanium layer is oxidized. The oxidized silicon germanium layer forms germanium nanocrystals surrounded by a tunnel oxide layer
Data Source
AI summary
A method of fabricating nanocrystal memory array includes stacking a silicon layer and a silicon germanium layer on a wafer. A gate oxide layer over is then formed on the silicon layer and the silicon germanium layer. Next, a gate layer is deposited on the gate oxide layer. Subsequently, the gate layer, gate oxide layer and the silicon germanium layer are patterned. Finally, the silicon germanium layer is oxidized. The nanocrystal is sandwiched in between the gate and the silicon layer, and the gate oxide layer surrounds the nanocrystal.