Nanocrystalline Silicon Formation via Amorphous Layer Annealing
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Solution Overview
Problem
Conventional technologies face challenges in forming high-quality nano-sized silicon structures for semiconductor devices, particularly at smaller device sizes, due to limitations in dielectric material formation and process constraints.
Innovation Solution
A method involving the formation of nanocrystalline silicon structures through a thermal treatment process of amorphous silicon material, deposited on a dielectric layer, which includes steps like surface cleaning, oxidizing, and high-temperature annealing to create nano-sized crystalline structures suitable for integrated circuits and other applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional technologies are used to form silicon materials for capacitor structures, then the manufacturing process is simple, but it is difficult to form high quality nano-sized silicon structures
Solution Approach 1:
The patent changes the physical and chemical parameters of the silicon material formation process by using amorphous silicon as the starting material and applying specific thermal treatment conditions (temperature, time, atmosphere) to transform it into nanocrystalline silicon. This parameter change enables the formation of high-quality nano-sized silicon structures that conventional direct deposition methods cannot achieve.
Solution Approach 2:
The patent utilizes phase transition by transforming amorphous silicon into nanocrystalline silicon through controlled thermal treatment. This phase transition from amorphous to crystalline state at the nanoscale allows the formation of high-quality nano-sized silicon structures with improved electrical and structural properties, resolving the quality issue while maintaining process feasibility.
2Productivity
If device geometry is reduced to increase circuit density, then more devices can be fabricated on each wafer, but process limitations prevent further scaling
Solution Approach 1:
The patent employs parameter changes by controlling the thickness of the amorphous silicon layer and the thermal treatment conditions to precisely control the size and quality of the resulting nanocrystalline structures. This enables the formation of high-quality nano-sized silicon structures at dimensions required for advanced circuit density scaling, overcoming conventional process limitations.
3Manufacturing precision
If thermal treatment process is applied to amorphous silicon material, then nanocrystalline silicon structures are formed, but process complexity increases
Solution Approach 1:
The patent uses amorphous silicon as an intermediary material that can be deposited using conventional techniques and then transformed into nanocrystalline silicon through thermal treatment. This intermediary approach allows the use of existing manufacturing infrastructure while achieving the complex nanocrystalline structure formation, thereby managing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances device yields and is compatible with conventional processes, allowing for the formation of nano-sized crystalline materials without significant equipment modifications, improving circuit density and performance.
Implementation Method 1
subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrystalline silicon structures
Implementation Method 2
cause formation of a plurality of nanocrystalline silicon structures derived from the thickness of amorphous silicon material
Implementation Method 3
subjecting the amorphous silicon material to a thermal treatment process
Data Source
AI summary
A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. In a specific embodiment, the present invention includes providing a semiconductor substrate including a surface region. The method includes forming an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region according to a specific embodiment. The method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrystalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers.