Nanodevice Active Region Spacing for Stronger Backside Power Vias
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Solution Overview
Problem
As semiconductor devices scale down, nanosheets interfere with each other, and forming connections to a backside power network becomes increasingly difficult.
Innovation Solution
The solution involves creating different dimensions across active regions for nanodevices, specifically enlarging the space between certain sections of transistors to facilitate a stronger via connection to the backside power rail by varying the distances between transistor sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheets are scaled down and placed closer together to increase device density, then device integration density is improved, but nanosheets interfere with each other and connection formation to backside power network becomes difficult
Solution Approach 1:
The active region is segmented into multiple sections (first section, second section, third section) with different spacing configurations. The first and third sections have smaller spacing to maintain device density, while the second section has larger spacing to facilitate via formation and backside power network connection, resolving the conflict between density and connectivity.
Solution Approach 2:
Different spacing dimensions are applied to different sections of the active region. The first distance and third distance are smaller for high-density transistor placement, while the second distance is larger to enable robust via formation. This local variation in spacing quality allows simultaneous optimization of both device density and power network connectivity.
2Productivity
If uniform small spacing is used across all sections to maximize device density, then integration density is improved, but via formation to backside power rail becomes difficult and weaker
Solution Approach 1:
The active region employs asymmetric spacing where the second distance between adjacent active regions is greater than the first and third distances. This asymmetric configuration creates a localized larger space in the second section specifically for via formation, enabling stronger backside power rail connections without compromising the overall high device density achieved through smaller spacing in other sections.
Data Source
AI summary
According to the embodiment of the present invention, a semiconductor device includes a first nanodevice and a second nanodevice. The second nanodevice is located adjacent to and parallel to the first nanodevice along a first axis. The first nanodevice and the second nanodevice each include a first section, a second section, and a third section. A first gate cut region is located between the first sections of the first nanodevice and the second nanodevice. A middle gate cut region is located between the second sections of the first nanodevice and the second nanodevice. A third gate cut region is located between the third sections of the first nanodevice and the second nanodevice. The middle gate cut region has different dimensions along a second axis than the first gate cut region and the third gate cut region.