Nanodot Floating Gate Isolation Trench Formation
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Solution Overview
Problem
Current fabrication techniques are insufficient for integrating nanostructure-based charge storage regions in memory devices, particularly in scaling down device dimensions and preventing charge trapping in undesired regions between cells.
Innovation Solution
A method involving the formation of a tunnel oxide layer, a floating gate layer with embedded nanodots in a dielectric material, and a blocking dielectric layer over the nanodots, followed by the creation of isolation trenches and filling them with dielectric material, ensuring precise alignment and containment of nanodots within memory cell stacks to prevent charge leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication techniques are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to insufficient alignment and containment of nanodots
Solution Approach 1:
The patent applies preliminary action by forming the blocking dielectric layer over the nanodots before forming the control gate. This sequence ensures that the nanodots are contained within the blocking dielectric layer prior to subsequent processing steps, preventing charge trapping in undesired regions and improving alignment precision without requiring complex post-fabrication adjustments
Solution Approach 2:
The patent segments the gate structure into distinct functional layers: a blocking dielectric layer containing the nanodots and a control gate layer formed thereover. This segmentation allows independent optimization of each layer's properties and simplifies the fabrication process by enabling separate formation steps with standard techniques
2Productivity
If device dimensions are scaled down to increase storage capacity, then productivity is improved, but manufacturing precision deteriorates due to difficulty in containing nanodots in smaller regions
Solution Approach 1:
The patent implements nesting by placing the nanodots within the blocking dielectric layer, which is itself positioned between the channel and the control gate. This nested structure ensures that even as device dimensions scale down, the nanodots remain contained within the blocking dielectric layer, maintaining manufacturing precision while enabling higher storage capacity through smaller feature sizes
3Quantity of substance
If nanodots are used as charge storage elements, then storage capacity is improved, but charge trapping in undesired regions occurs due to insufficient containment
Solution Approach 1:
The patent extracts the nanodots from the continuous floating gate material and embeds them as discrete particles within the blocking dielectric layer. This extraction and embedding approach confines the charge storage function to specific locations within the blocking dielectric layer, preventing charge trapping in undesired regions while maintaining high storage capacity through the distributed nanodot array
Data Source
AI summary
Methods of fabricating a memory device include forming a tunnel oxide layer over a memory cell area of a semiconductor substrate, forming a floating gate layer over the tunnel oxide layer in the memory cell area, the floating gate layer comprising a plurality of nanodots embedded in a dielectric material, forming a blocking dielectric layer over the floating gate layer in the memory cell area, removing portions of the blocking dielectric layer, the floating gate layer, the tunnel oxide layer, and the semiconductor substrate in the memory cell area to form a first plurality of isolation trenches, and forming isolation material within the first plurality of isolation trenches.