Nanodot Memory Cell Charge Retention via Segmentation
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Solution Overview
Problem
The continued scaling down of floating gate memory devices increases the sensitivity of charge retention characteristics to defects in the tunnel oxide, which can lead to instability and data retention issues.
Innovation Solution
The use of nanodots as a floating gate in memory cells reduces sensitivity to defects by allowing adjacent nanodots to maintain charge even if one is affected, with a method involving deposition of nanodots over a first dielectric layer, encasing them in a second dielectric layer, and forming an intergate dielectric layer with patterned sidewalls, and using a spacing layer to fill voids created during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the tunnel oxide thickness is reduced to enable further scaling down of memory devices, then the device size is reduced, but the sensitivity to defects in the tunnel oxide increases and charge retention characteristics deteriorate
Solution Approach 1:
The patent divides the continuous floating gate into discrete nanodots separated by dielectric material. This segmentation allows individual nanodots to be isolated from each other, so that defects in the tunnel oxide affect only adjacent nanodots rather than the entire floating gate. The nanodots are formed by depositing material and patterning it into discrete structures, creating independent charge storage units that maintain reliability even as device size scales down.
2Reliability
If nanodots are used as floating gate to reduce sensitivity to defects, then charge retention is improved, but the device structure and fabrication process become more complex
Solution Approach 1:
The patent embeds nanodots within a matrix of dielectric material, creating a nested structure where the floating gate functionality is contained within the intergate dielectric layer. The nanodots are formed by depositing conductive material and then embedding it in dielectric layers, with the dielectric material surrounding and isolating each nanodot. This nested approach integrates the complex nanodot structure into the existing memory cell architecture without requiring completely new fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge retention and reduces power consumption by minimizing the impact of defects, allowing for more reliable and efficient data storage in smaller semiconductor devices.
Implementation Method 1
The improved characteristics exhibited by the nanodot device may be attributed to Coulomb blockage at room temperature when nanodots smaller than about ten (10) nanometer (nm) in diameter are used for a floating gate, with the result that a threshold voltage shift may be quantized and multi-bit information may be stored.
Data Source
AI summary
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.