Nanoelectrode Array Addressing for High-Throughput DNA Synthesis
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Solution Overview
Problem
Current nanoelectrode arrays face challenges in achieving high synthesis throughput and efficient molecular data storage due to the need for addressing a vast number of electrodes simultaneously, which requires significant space, power, and time, making it difficult to achieve commercially relevant writing speeds.
Innovation Solution
The use of nanoelectrodes with access transistors and storage circuits allows for dense, compact arrays where each nanoelectrode can be individually addressed and set quickly, with low power and voltage, enabling parallel synthesis of molecules like DNA, and employing strategies from dynamic random-access memory (DRAM) to manage electrode potentials and reaction conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If arrays of about one billion electrodes are used to achieve high synthesis throughput, then productivity is improved, but device complexity and space requirements worsen significantly
Solution Approach 1:
The patent segments the control of one billion electrodes into manageable units by implementing hierarchical addressing schemes and dividing the array into smaller sub-arrays or blocks that can be controlled independently, reducing the complexity of addressing each individual electrode directly
Solution Approach 2:
The patent introduces additional control dimensions beyond simple electrode addressing, such as temporal multiplexing (controlling electrodes at different times) and spatial hierarchy (grouping electrodes into regions), effectively adding dimensions to the control space to manage the vast number of electrodes
2Productivity
If arrays of about one billion electrodes are used to achieve high synthesis throughput, then productivity is improved, but the space required increases dramatically
Solution Approach 1:
The patent implements nested hierarchical structures where electrodes are organized into groups, groups into regions, and regions into the full array, allowing compact packaging of one billion electrodes by nesting control structures within each other, similar to nested dolls
Solution Approach 2:
The patent transitions from two-dimensional array layout to three-dimensional integration by stacking multiple electrode layers or using vertical interconnection structures, effectively utilizing the third dimension to reduce the footprint area required for one billion electrodes
3Productivity
If vast numbers of electrodes are addressed simultaneously, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic or pulsed addressing schemes where electrodes are activated in time-multiplexed sequences rather than all simultaneously, allowing the system to achieve the same overall productivity while consuming less power at any given moment by cycling through electrode activation
Solution Approach 2:
The patent activates only the subset of electrodes needed for current synthesis operations rather than all electrodes simultaneously, using partial action to reduce power consumption while maintaining productivity by dynamically allocating electrode resources based on demand
Data Source
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Figure 8
AI summary
In a first aspect, the present invention relates to a system for addressing nanoelectrodes (30-33) in a nanoelectrode array (20), the system comprising an array of electrode cells (60), each electrode cell (60) comprising: (i) an access transistor (70) having a gate resistively coupled to a word line (71), a source resistively coupled to a bit line (72), and a drain; and (ii) a storage circuit (80) resistively coupled to the drain and comprising a nanoelectrode (30-33).