Nano-FET Gate Stack Processing for DOI Oxide Removal Control

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Solution Overview

Problem

Conventional methods for semiconductor device fabrication face challenges such as residual oxide remaining after disposable oxide interposer (DOI) removal, over-etching leading to source/drain epitaxial damage, and junction underlapping issues, which affect the integration density and performance of nano-FETs.

Innovation Solution

A method involving a tilt implant or plasma doping approach is used to enhance the etching rate of DOI oxide, allowing for precise control over doping and etching processes to mitigate residual oxide and over-etching, while enhancing doping at the extension region and silicon etching rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional DOI removal methods are used, then the DOI oxide is removed, but residual oxide remains and source/drain epitaxial damage occurs

Engineering Contradiction:
ImproveDOI removal completenessVSAvoidsource/drain epitaxial damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by performing implantation to increase the etch rate of the DOI oxide before the DOI removal etching step. This pre-treatment modifies the DOI oxide properties in advance, enabling complete removal without requiring aggressive etching that would damage the source/drain epitaxial regions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the etch rate parameter of the DOI oxide through implantation treatment. By modifying the physical/chemical properties of the DOI oxide via implantation, the etch rate is increased, allowing selective removal of DOI oxide while protecting adjacent sensitive structures from damage.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If aggressive etching is used to remove DOI oxide completely, then residual oxide is eliminated, but source/drain epitaxial damage occurs

Engineering Contradiction:
Improveresidual oxide eliminationVSAvoidsource/drain epitaxial integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies local quality by creating a differentiated etch rate in the DOI oxide through implantation. The DOI oxide acquires enhanced etchability locally, while the source/drain epitaxial regions maintain their original properties. This allows selective removal of DOI oxide without affecting the integrity of adjacent sensitive structures.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The implantation treatment acts as an intermediary that modifies the DOI oxide properties to facilitate its selective removal. The implantation creates a intermediate state in the DOI oxide with increased etch rate, serving as a mediator between the DOI oxide and the removal etching process, enabling complete removal without aggressive conditions.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If standard doping processes are used, then doping is applied uniformly, but junction underlapping issues occur and extension region doping is insufficient

Engineering Contradiction:
Improvedoping process simplicityVSAvoidjunction alignment and doping distribution
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent applies asymmetry by using tilted implantation angles to create non-uniform doping distributions. The tilt angle causes dopants to preferentially enter specific regions, enabling enhanced doping in the extension regions and proper junction formation without requiring complex multi-step alignment processes.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent introduces angular dimensionality by using tilted implantation instead of normal incidence doping. This adds a dimensional parameter (angle) to the doping process, enabling precise control over dopant distribution in the extension regions and effective mitigation of junction underlapping without complicating the operational sequence.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces the likelihood of residual material and improves the efficiency and precision of nano-FET formation by preventing over-etching and enhancing doping, resulting in improved channel mobility and reduced electrical resistance.

Implementation Method 1

performing a first implantation process on the disposable material and the second semiconductor layers

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

A method involving a tilt implant or plasma doping approach is used to enhance the etching rate of DOI oxide

Methodology Applied
Scientific EffectPlasma doping: Plasma

Data Source

PatentUS20250351486A1Semiconductor device and method
Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250351486A1 patent drawing
  • US20250351486A1 patent drawing
  • US20250351486A1 patent drawing

AI summary

In an embodiment, a method may include forming a multi-layer stack over a substrate. The multi-layer stack has alternating layers of first semiconductor layers and second semiconductor layers. The method may also include removing the first semiconductor layers. Furthermore, the method may include forming a disposable material between the second semiconductor layers. In addition, the method may include performing a first implantation process on the disposable material and the second semiconductor layers. Moreover, the method may include forming source/drain regions adjacent to the second semiconductor layers and the disposable material. The method may also include replacing the disposable material with a metal gate structure.