Nano-FET Gate Structures With Sacrificial Layer Work Function Tuning
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating components efficiently while maintaining performance, particularly in forming gate structures for p-type and n-type devices without degrading their performance.
Innovation Solution
The method involves forming work function tuning layers for n-type devices before p-type devices, using a sacrificial layer to prevent contamination, and employing flowable chemical vapor deposition for improved deposition profiles and gap filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If work function tuning layers are formed for both p-type and n-type devices in the same process, then manufacturing efficiency is improved, but contamination occurs and device performance degrades
Solution Approach 1:
The patent divides the work function tuning process into separate sequential steps for p-type and n-type devices, using a sacrificial layer to segment the deposition zones. This prevents cross-contamination while maintaining manufacturing efficiency by organizing the complex multi-layer structure into manageable segments that can be processed systematically.
Solution Approach 2:
The sacrificial layer acts as an intermediary barrier during the deposition process, temporarily blocking the deposition of work function tuning material to specific regions. This mediator prevents direct contamination between p-type and n-type device areas, allowing both device types to be processed in the same manufacturing run without performance degradation.
2Ease of manufacture
If conventional deposition methods are used, then process simplicity is maintained, but deposition profiles are poor and gap filling is inadequate
Solution Approach 1:
The patent employs flowable chemical vapor deposition with controlled flow rates and deposition parameters to achieve superior deposition profiles and complete gap filling. By optimizing parameters such as precursor flow rates, temperature, and pressure, the process achieves high precision material deposition while maintaining reasonable process complexity through systematic parameter control.
3Productivity
If feature sizes are reduced to increase integration density, then more components are integrated per area, but additional manufacturing challenges and performance degradation occur
Solution Approach 1:
The patent implements a nested multi-layer structure with sacrificial layers, work function tuning layers, and gate electrode layers arranged in concentric nested configurations. This nesting approach allows precise control of threshold voltages for both p-type and n-type devices within the same integrated structure, enabling high integration density while managing manufacturing complexity through hierarchical organization.
Solution Approach 2:
The sacrificial layer is formed in advance before the work function tuning layers are deposited. This preliminary action establishes the spatial boundaries and prevents contamination before the critical deposition steps occur, addressing manufacturing challenges proactively rather than reactively, and enabling successful miniaturization with maintained device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the control of threshold voltages and prevents performance degradation, ensuring seamless integration and improved performance of nano-FETs.
Implementation Method 1
a sacrificial layer to prevent contamination
Implementation Method 2
employing flowable chemical vapor deposition for improved deposition profiles and gap filling
Data Source
AI summary
A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.