Nano-FET Inner Spacer Formation Using Differential Etch Layers
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in the fabrication process that affect yield and reliability of nano-FETs, particularly in forming channel regions and gate structures.
Innovation Solution
A method involving the formation of a stack of alternating semiconductor layers over a substrate, patterning to create nanostructures, and using sacrificial materials with distinct etch rates to form notches and inner spacers, followed by epitaxial growth of source/drain regions and replacement of the sacrificial material with a gate structure, enhancing the fabrication process of nano-FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but fabrication challenges increase affecting yield and reliability
Solution Approach 1:
The patent divides the gate formation process into multiple stages using a multi-layer sacrificial material structure. The sacrificial material is segmented into different layers with distinct etch rates, allowing sequential formation of notches and inner spacers. This segmentation enables precise control over the gate structure formation at reduced feature sizes, thereby maintaining reliability while achieving high integration density.
Solution Approach 2:
The patent introduces sacrificial material as an intermediary substance to facilitate the formation of complex gate structures. The sacrificial material layers act as temporary structures that guide the self-aligned formation of notches and inner spacers during etching processes. After serving their structural guidance function, these intermediary materials are selectively removed, enabling precise gate formation without direct complex patterning at the nanoscale.
2Ease of manufacture
If conventional fabrication processes are used for nano-FETs, then manufacturing is simpler, but damage to nanostructure channels occurs reducing yield
Solution Approach 1:
The patent applies preliminary protective actions by forming inner spacers within notches of the sacrificial material structure before the main etching processes. These pre-formed inner spacers act as protective barriers that prevent damage to the nanostructure channels during subsequent etching and fabrication steps. The inner spacers are positioned in advance to counteract potential mechanical or chemical damage that would otherwise occur during conventional fabrication processes.
Solution Approach 2:
The patent performs preliminary structuring by forming notches and inner spacers in the sacrificial material before the actual gate formation. This preliminary action establishes a self-aligned template that guides subsequent fabrication steps, eliminating the need for additional alignment-critical patterning steps that would increase complexity. The preliminary structure enables simple, direct formation of the final gate while protecting the channels.
3Manufacturing precision
If multi-layer sacrificial material with distinct etch rates is used, then precise shaping of inner spacers is achieved, but device complexity increases
Solution Approach 1:
The patent employs self-service mechanisms where the multi-layer sacrificial material structure performs multiple functions automatically through its inherent properties. The layers with distinct etch rates self-organize during etching processes to form notches and inner spacers without requiring additional complex patterning steps. The structure serves itself by using differential etching to automatically create the precise geometries needed, eliminating the need for multiple separate fabrication operations.
Solution Approach 2:
The patent utilizes parameter changes in the sacrificial material layers, specifically varying the etch rates of different layers. By changing this material parameter, the etching process automatically produces different geometries (notches vs. inner spacers) from the same multi-layer structure. This parameter variation enables precise shaping through a single integrated process rather than multiple discrete steps, managing complexity while achieving high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the yield and reliability of nano-FETs by allowing for precise shaping of inner spacers and reducing damage to nanostructure channels, resulting in improved performance.
Implementation Method 1
The sacrificial material is etched to form notches in the sacrificial material
Implementation Method 2
Source/drain regions are then epitaxially grown over the sidewalls of the nanostructure channels
Data Source
AI summary
A method includes forming a first semiconductor layer and a second semiconductor layer over a substrate; performing a first etch process on the first semiconductor layer and the second semiconductor layer to form a first fin; forming a gate structure across the first fin; performing a second etch process to form a first recess and a second recess in the first fin; removing the first semiconductor layer; depositing a first material layer along exposed surfaces of the second semiconductor layer and the substrate; depositing a second material layer over the first material layer; etching the first material layer and the second material layer to form a third recess, a first etch rate of the first material layer being different than a second etch rate of the second material layer; forming an inner spacer in the third recess; and forming a source/drain region in the first recess.