Dual-Layer Nano-FET Inner Spacer for Dummy Gate Stability
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, issues arise with pattern loading effects during the formation of nano-FETs, leading to bending or tilting of boundary dummy gates due to uneven sidewall spacer deposition, which can compromise device integrity.
Innovation Solution
Employing a two-layer inner spacer structure with mismatched coefficients of thermal expansion (CTE) to counteract compressive stress on boundary dummy gates, ensuring they remain stable during cooling and patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but pattern loading effects cause bending or tilting of boundary dummy gates due to uneven sidewall spacer deposition
Solution Approach 1:
The patent changes the physical parameters of the spacer structure by introducing a dual-layer configuration with different materials having distinct coefficients of thermal expansion. This parameter change allows the spacer to compensate for thermal stress during cooling, preventing the boundary dummy gate from bending or tilting while maintaining the reduced minimum feature sizes needed for high integration density
Solution Approach 2:
The patent employs composite materials by creating a dual-layer spacer structure where each layer is made of different materials (first spacer material and second spacer material) with mismatched coefficients of thermal expansion. This composite structure generates differential thermal stress that counteracts the compressive stress causing gate bending, thereby maintaining manufacturing precision at scaled dimensions
2Device complexity
If single-layer spacer structures are used for simplicity, then device fabrication is easier, but compressive stress causes boundary dummy gates to bend during cooling
Solution Approach 1:
The patent introduces a parameter change by transitioning from a single-layer spacer to a dual-layer spacer with different materials. This structural parameter change enables the spacer to manage thermal stress effectively, preventing boundary dummy gate bending and improving device reliability without significantly complicating the fabrication process
Solution Approach 2:
The patent exploits thermal expansion principles by selecting spacer materials with mismatched coefficients of thermal expansion. During cooling, the differential contraction between the two spacer layers generates internal stress that counteracts the compressive stress on the boundary dummy gate, thereby maintaining gate stability and preventing bending
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-layer inner spacer structure effectively prevents bending of boundary dummy gates, maintaining device integrity and enhancing the reliability of nano-FETs by balancing thermal expansion stresses.
Implementation Method 1
The material of the first inner spacer layer and second inner spacer layer may be different, such that a coefficient of thermal expansion (CTE) of the first inner spacer layer is different from a CTE of the second inner spacer layer
Data Source
AI summary
Embodiments utilize a two layer inner spacer structure during formation of the inner spacers of a nano-FET device. The materials of the first inner spacer layer and second inner spacer layer can be selected to have a mismatch in their coefficients of thermal expansion (CTE). As the structure cools after deposition, the inner spacer layer which has a larger CTE will exhibit compressive stress on the other inner spacer layer, however, because the two layers have a common interface, the layer with the smaller CTE will exhibit a counter acting tensile stress.