Nano-FET Gate Stack Formation With Rounded Nanosheet Corners
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in maintaining device performance due to issues such as increased channel resistance and reduced carrier mobility, particularly in nano-FETs, which are exacerbated by manufacturing defects and impurities during the replacement of nanostructures with gate stacks.
Innovation Solution
The process involves forming first nanostructures that are subsequently replaced with a sacrificial material to define openings, which are then filled with a gate stack, while trimming the nanostructures to remove impurities and round corners, enhancing deposition windows and reducing gate stack gaps, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but device performance deteriorates due to increased channel resistance and reduced carrier mobility
Solution Approach 1:
The patent applies curvature to the corner regions of nanostructures by performing a trimming process that increases the radius of corner regions to a specified range (e.g., 0.5 nm to 2 nm). This curvature modification improves the deposition window for gate stacks, reduces gaps in the gate stack, and enhances carrier mobility while reducing channel resistance, thereby maintaining device performance despite reduced feature sizes
Solution Approach 2:
The patent performs a trimming process on nanostructures before forming the gate stack. This preliminary action removes impurities from the surface of the first nanostructures and pre-rounds the corner regions, creating an optimized surface that improves subsequent gate stack deposition and reduces defects, thereby preserving device performance at scaled dimensions
2Ease of operation
If nanostructures are replaced with gate stacks to form functional devices, then device functionality is achieved, but manufacturing defects and impurities increase, degrading device performance
Solution Approach 1:
The patent extracts and removes impurities from the surface of the first nanostructures through a trimming process before gate stack formation. This extraction of harmful contaminants prevents manufacturing defects and maintains high device performance, enabling functional devices to be formed without the performance degradation that would otherwise result from the replacement process
Solution Approach 2:
The trimming process is performed as a preliminary step before gate stack formation to remove impurities and optimize the nanostructure surface. This preliminary cleaning and rounding action prevents manufacturing defects from occurring during the subsequent gate stack deposition process, thereby maintaining manufacturing precision and device performance
Data Source
AI summary
A method includes removing first nanostructures from a plurality of nanostructures, the plurality of nanostructures comprising the first nanostructures alternatingly stacked with second nanostructures. After removing the first nanostructures, the method includes performing a trimming process on the second nanostructures, wherein the trimming process increases a curvature of at least a first corner of the second nanostructures. The method further includes forming a sacrificial material between the second nanostructures and replacing the sacrificial material with a gate stack.