Nano-FET P-Type Source/Drain Silicon Cap for Etch Protection
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Solution Overview
Problem
The protection of p-type source/drain regions in nano-FETs during the manufacturing process is inadequate, particularly against chlorine-containing etchants, leading to potential damage and reduced reliability.
Innovation Solution
A silicon cap layer, specifically a high boron-doped silicon layer, is introduced as a protective barrier with a controlled thickness of 2-6 nanometers to cover the underlying p-type epitaxial structure, enhancing protection against etching chemicals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a protection layer is used to cover p-type source/drain regions, then the regions are protected during manufacturing, but the protection layer may not provide sufficient coverage against chlorine-containing etchants
Solution Approach 1:
The patent applies composite materials by combining a silicon cap layer with a protection layer to create a multi-layer protective structure. The silicon cap layer (2-6 nm thick) provides etch resistance against chlorine-containing etchants, while the protection layer offers additional coverage. This composite approach resolves the contradiction by providing superior protection compared to a single protection layer alone.
Solution Approach 2:
The patent changes the physical and chemical parameters of the cap layer by using high boron doping concentration (1×10^19 to 1×10^21 atoms/cm³) and controlling the thickness (2-6 nm). These parameter changes enhance the etch resistance of the silicon cap layer, enabling it to effectively protect against chlorine-containing etchants that would otherwise damage the p-type source/drain regions.
2Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated, but additional manufacturing problems arise
Solution Approach 1:
The patent applies preliminary action by forming the silicon cap layer on the p-type source/drain regions before the chlorine-containing etching process. This pre-formed protective layer prevents etchant damage during subsequent manufacturing steps, addressing the increased fabrication challenges that arise when minimum feature sizes are reduced for higher integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The silicon cap layer significantly enhances the integrity of p-type source/drain regions, ensuring reliable fabrication and potentially higher performance of nano-FETs by providing enhanced etch resistance.
Implementation Method 1
The silicon cap layer significantly enhances the integrity of p-type source/drain regions, ensuring reliable fabrication and potentially higher performance of nano-FETs by providing enhanced etch resistance
Data Source
AI summary
In an embodiment, a method may include forming a multi-layer stack over a substrate, the multi-layer stack having alternating layers of first semiconductor layers and second semiconductor layers. The method may also include forming first source/drain regions adjacent the first semiconductor layers and the second semiconductor layers in a first region, the first source/drain regions having a cap layer, forming a protection layer over the first source/drain regions, forming second source/drain regions adjacent the first semiconductor layers and the second semiconductor layers in a second region, removing the protection layer from over the first source/drain regions, replacing the first semiconductor layers in the first region with a first metal gate structure, and replacing the first semiconductor layers in the second region with a second metal gate structure.