Nanostructure-FET Source/Drain Spacing for Leakage Isolation
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges such as increased leakage current due to electrical coupling between semiconductor fins and source/drain regions, leading to performance issues in nanostructure field-effect transistors (nanostructure-FETs).
Innovation Solution
The formation of spacers at the bottom of source/drain recesses and on underlying semiconductor fins reduces electrical coupling by creating gaps between the fins and source/drain regions, using sacrificial spacers and insulating fins to block leakage currents and prevent parasitic channel operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but electrical coupling between semiconductor fins and source/drain regions increases leading to higher leakage currents
Solution Approach 1:
The patent divides the source/drain structure into multiple segments by introducing air gaps between the source/drain regions and the semiconductor fins. This segmentation breaks the continuous electrical coupling path into discrete sections, reducing parasitic channel formation and leakage currents while maintaining the compact structure needed for high integration density
Solution Approach 2:
The patent introduces air gaps as intermediary elements between the source/drain regions and the semiconductor fins. These air gaps act as electrical isolators that prevent direct electrical coupling, thereby reducing leakage currents and parasitic channel effects while allowing the components to remain in close proximity for high integration density
2Area of stationary object
If source/drain regions are formed closer to semiconductor fins to reduce device area, then integration density improves, but electrical coupling increases causing higher leakage currents
Solution Approach 1:
The patent addresses the area-leakage current tradeoff by introducing a new dimensional element (air gaps) in the vertical and lateral spacing between components. This allows source/drain regions to be positioned close to fins for minimal area while the air gaps provide electrical isolation in the intermediate space, effectively decoupling the area reduction benefit from the leakage current penalty
Data Source
AI summary
In an embodiment, a device includes: a semiconductor fin extending from a semiconductor substrate; a nanostructure above the semiconductor fin; a source/drain region adjacent a channel region of the nanostructure; a bottom spacer between the source/drain region and the semiconductor fin; and a gap between the bottom spacer and the source/drain region.