Nano-FET Sidewall Spacer Expansion to Reduce Seams and Dishing
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Solution Overview
Problem
In the semiconductor industry, the reduction of minimum feature sizes in nano-FET manufacturing leads to issues such as seam formation and dishing of sidewall spacers, which affect the performance and reliability of nano-FETs.
Innovation Solution
A process is developed to treat the sidewall spacers in nano-FETs to reduce or eliminate seams and dishing, involving an oxidation anneal and dry anneal to expand and crosslink the spacer material, thereby improving the effectiveness of the spacers and reducing the risk of shorting between source/drain regions and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but seam formation and dishing of sidewall spacers occur
Solution Approach 1:
The patent applies oxidation anneal and dry anneal processes to change the physical and chemical parameters of the sidewall spacer material. These thermal treatments modify the material properties to reduce seam formation and dishing, thereby maintaining manufacturing precision while enabling continued scaling for higher integration density
Solution Approach 2:
The patent uses composite material structures consisting of multiple layers with different materials (e.g., silicon nitride, silicon oxide, silicon carbide) to form the sidewall spacers. This multi-layer composite approach allows each layer to contribute different properties that collectively prevent seam formation and dishing, resolving the contradiction between scaling and spacer quality
2Reliability
If seam formation and dishing occur in sidewall spacers, then manufacturing defects increase, but current efficiency and reliability of nano-FETs decrease
Solution Approach 1:
The patent performs oxidation anneal and dry anneal treatments on the sidewall spacers before they are used in subsequent manufacturing steps. This preliminary action pre-empts potential seam formation and dishing issues, ensuring uniform spacer quality that maintains both manufacturing precision and final device reliability
Solution Approach 2:
The patent converts the potential harm of seam formation and dishing into a benefit by using controlled oxidation and dry anneal processes. These processes intentionally modify the spacer material structure to eliminate defects, transforming what would be harmful manufacturing variations into improved spacer uniformity and enhanced device reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process enhances the current efficiency (Ceff) of nano-FETs by reducing dishing and seam formation, leading to improved performance and reliability by increasing the lateral thickness and reducing the k-value of the spacer layer, thus preventing shorting and enhancing insulating properties.
Implementation Method 1
involving an oxidation anneal and dry anneal to expand and crosslink the spacer material
Implementation Method 2
involving an oxidation anneal and dry anneal to expand and crosslink the spacer material
Data Source
AI summary
Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.