Two-Tier Under-Epitaxy Isolation for Nano-FET Leakage Control
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Solution Overview
Problem
Current semiconductor devices face issues of current leakage and capacitance between source/drain regions due to contact with semiconductor material, particularly at the bottom of recesses in nano-FETs, which affect integration density and performance.
Innovation Solution
A low-k insulation material is formed at the bottom of recesses before forming source/drain regions, followed by an upper isolation layer to create a trench isolation structure, reducing current leakage and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source/drain regions are formed directly in recesses without insulation material, then manufacturing process is simpler, but current leakage and capacitance occur due to contact with semiconductor material
Solution Approach 1:
The patent applies preliminary action by forming the lower isolation structure (first insulating film) at the bottom of the recess before forming the source/drain regions. This pre-established insulation layer prevents current leakage and reduces capacitance between source/drain regions, addressing the reliability issue before the problematic contact can occur during device operation.
Solution Approach 2:
The patent introduces an intermediary material (insulating material forming the lower isolation structure) between the source/drain regions and the semiconductor substrate. This intermediary layer acts as a mediator that electrically isolates the source/drain regions from the substrate, preventing harmful current leakage paths and reducing parasitic capacitance while allowing the source/drain regions to function properly.
2Reliability
If insulation material is added at the bottom of recesses, then current leakage and capacitance are reduced, but device structure becomes more complex
Solution Approach 1:
The patent segments the isolation structure into distinct functional layers: a lower isolation structure (first insulating film) at the bottom of the recess and an upper isolation structure (second insulating film) filling the remaining recess space. This segmentation allows each layer to perform its specific function - the lower layer provides critical electrical isolation at the substrate interface, while the upper layer provides mechanical support and completes the isolation - making the overall complex structure manageable and effective.
Solution Approach 2:
The patent applies local quality by providing different isolation structures at different locations within the recess. The lower isolation structure is specifically positioned at the bottom where current leakage and capacitance problems occur, while the upper isolation structure fills the remaining space. This localized approach concentrates the insulation functionality where it is most needed to prevent harmful effects, rather than uniformly insulating the entire recess.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes current leakage and capacitance, enhancing the integration density and performance of nano-FETs by improving insulation and isolation in semiconductor devices.
Implementation Method 1
depositing a first insulating film in the recess to form a lower isolation structure
Implementation Method 2
depositing a second insulating film in the recess over the first insulating film to form an upper isolation structure
Data Source
AI summary
Embodiments provide a two-tiered trench isolation structure under the epitaxial regions (e.g., epitaxial source/drain regions) of a nano-FET transistor device, and methods of forming the same. The first tier provides an isolation structure with a low k value. The second tier provides an isolation structure with a higher k value, with material greater density, and greater etch resistivity than the first tier isolation structure.