Nanofin Transistors via Solid Phase Epitaxy
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Solution Overview
Problem
Conventional transistor structures face challenges in scaling down device size and increasing density due to difficulties in forming shallow junctions and high doping levels, which lead to increased leakage current and reduced carrier mobility, particularly in deep sub-micron MOSFET technology.
Innovation Solution
The development of nanofin transistors using solid phase epitaxy (SPE) to grow ultrathin semiconductor fins on a crystalline substrate, with a surrounding gate structure, allowing for dimensions smaller than lithographic limits and improved control over the transistor channel, reducing sub-threshold leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional implantation and diffusion techniques are used to form shallow junctions, then junction depth can be reduced, but manufacturing precision deteriorates due to difficulty in forming junctions with depth much less than channel length
Solution Approach 1:
The patent changes the manufacturing approach from conventional implantation and diffusion to selective area epitaxial growth. This parameter change enables precise control of junction depth at the nanoscale level, allowing junction depths much less than channel length to be formed with high precision. The epitaxial growth process provides atomic-layer control that conventional techniques cannot achieve.
Solution Approach 2:
The patent replaces the mechanical implantation and diffusion processes with a chemical epitaxial growth process. This substitution enables better control over junction depth and profile, as epitaxial growth can be precisely controlled through temperature, pressure, and gas flow parameters, achieving manufacturing precision that mechanical methods cannot provide.
2Reliability
If extremely high levels of channel doping are used to suppress short-channel effects, then short-channel effects are suppressed, but carrier mobility is reduced
Solution Approach 1:
The patent applies local quality by creating vertically-oriented channels with surrounding gates that provide enhanced electric field control specifically in the channel region. This localized control suppresses short-channel effects without requiring high doping levels throughout the device, thereby maintaining carrier mobility. The surrounding gate structure provides strong electrostatic control over the channel.
Solution Approach 2:
The patent transitions from planar channels to vertically-oriented channels, adding a dimensional change that improves electrostatic control. The vertical orientation allows surrounding gates to control the channel from multiple directions, providing superior suppression of short-channel effects without the need for high doping, thus preserving carrier mobility.
3Ease of manufacture
If conventional photolithography is used to define transistor dimensions, then manufacturing is simplified, but device size cannot be reduced below lithographic limits
Solution Approach 1:
The patent uses self-aligned spacer structures as intermediaries to define the vertical channel dimensions. These spacers are formed through atomic layer deposition and etch processes that provide precise dimensional control at the nanoscale, enabling device dimensions below conventional lithographic limits while maintaining manufacturing simplicity through self-alignment.
Solution Approach 2:
The patent extracts the dimension-defining function from the photolithography step and transfers it to subsequent thin-film deposition and etch processes. This extraction allows the critical dimensions to be controlled by thin-film thickness (which can be controlled at the nanometer and sub-nanometer level) rather than by lithographic resolution, enabling smaller device dimensions.
4Object-generated harmful factors
If dual-gate or double-gate structures are used to screen drain electric field, then sub-threshold leakage is reduced, but device complexity increases
Solution Approach 1:
The patent merges the gate control functions into a single surrounding gate structure that encircles the vertical channel. This unified surrounding gate provides comprehensive electrostatic control and effective screening of drain electric fields from all directions, achieving superior sub-threshold leakage suppression while avoiding the complexity of multiple separate gates.
Solution Approach 2:
The patent transitions from planar gates to a three-dimensional surrounding gate structure. This dimensional change allows the gate to control the channel from all directions (top, bottom, and sides), providing superior electric field screening and sub-threshold leakage suppression with a single integrated structure rather than multiple planar gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nanofin transistors achieve reduced sub-threshold leakage and enhanced carrier mobility, improving performance and device density while maintaining lower power consumption and smaller sizes.
Implementation Method 1
grow ultrathin fins of semiconductor (e.g. silicon) from amorphous semiconductor (e.g. a-silicon) using solid phase epitaxy (SPE) on a crystalline substrate. The SPE process recrystallizes the amorphous semiconductor, using the crystalline substrate to seed the crystalline growth.
Data Source
AI summary
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.