Nanofin Transistors With Surrounding Gates For Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional transistor structures face challenges in scaling down device size due to difficulties in forming shallow junctions and high doping levels, which result in increased leakage current and reduced carrier mobility, particularly in deep sub-micron MOSFET technology.
Innovation Solution
The use of a sidewall spacer technique to etch ultrathin nanofins into a silicon substrate, forming nanofin transistors with surrounding gates, which allows for vertically-oriented channel regions and reduced sub-threshold leakage current by screening the electric field effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional implantation and diffusion techniques are used to form shallow junctions, then junction depth can be reduced, but manufacturing precision deteriorates due to difficulty in forming junctions with depth much less than channel length
Solution Approach 1:
The patent segments the channel structure into multiple vertical segments by creating nanofin structures with thicknesses of 10-50 nm. This segmentation allows the channel to be controlled in a vertical orientation, enabling better electric field management and reduced short-channel effects without requiring extremely shallow junctions formed by conventional horizontal implantation techniques.
Solution Approach 2:
The patent transitions from conventional horizontal channel structures to vertical nanofin structures, changing the dimensional orientation of the channel. This vertical orientation allows the gate to effectively control the channel through the thickness dimension, enabling precise control of carrier flow and reduced leakage current without being constrained by horizontal junction depth limitations.
2Reliability
If extremely high levels of channel doping are used to suppress short-channel effects, then short-channel effects are reduced, but carrier mobility deteriorates due to increased leakage and reduced carrier mobility
Solution Approach 1:
The patent changes the geometric parameters of the channel structure by creating nanofins with controlled thicknesses of 10-50 nm and vertical orientations. This parameter change allows effective gate control of the channel without requiring extremely high doping levels, thereby suppressing short-channel effects while maintaining lower doping levels that preserve carrier mobility and reduce leakage current.
Solution Approach 2:
The patent employs composite material structures combining the nanofin semiconductor material with gate materials and insulating layers. This composite structure enables effective electric field control through the vertical nanofin channel, achieving short-channel effect suppression through structural design rather than relying solely on high doping levels, thus maintaining better carrier mobility.
3Productivity
If transistor dimensions are scaled down to deep sub-micron region, then device density is increased, but sub-threshold leakage current increases due to small threshold voltage magnitudes
Solution Approach 1:
The patent utilizes vertical nanofin structures that extend upward from the substrate, changing from horizontal to vertical dimensioning. This vertical orientation allows the gate to control the channel through the thin thickness dimension (10-50 nm), providing effective electric field screening that reduces sub-threshold leakage current even as device dimensions are scaled down to increase density.
Solution Approach 2:
The patent creates highly localized control of the channel through the thin nanofin structure, where the gate electric field is concentrated across the small thickness dimension. This localized control enables effective suppression of sub-threshold leakage in specific regions while maintaining small overall device dimensions for high density integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of nanofin transistors with dimensions smaller than lithographic limits, reducing sub-threshold leakage and improving carrier mobility, thus addressing the limitations of conventional transistors in deep sub-micron scaling.
Implementation Method 1
The surrounding gate structure provides desirable control over the transistor channel, but the structure has been difficult to realize in practice. Some characteristics of the dual-gated and/or double-gated MOSFET are better than the conventional bulk silicon MOSFETs, because compared to a single gate, the two gates better screen the electric field generated by the drain electrode from the source-end of the channel.
Data Source
AI summary
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin is formed from a crystalline substrate. A first source/drain region is formed in the substrate beneath the fin. A surrounding gate insulator is formed around the fin. A surrounding gate is formed around the fin and separated from the fin by the surrounding gate insulator. A second source/drain region is formed in a top portion of the fin. Various embodiments etch a hole in a layer over the substrate, form sidewall spacers in the hole, form a fin pattern from the sidewall spacers, and etch into the crystalline substrate to form the fin from the substrate using a mask corresponding to the fin pattern. Other aspects are provided herein.