Parallel Semiconductor Nanofinger Transistor Gate Capacitance Reduction
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Solution Overview
Problem
Existing semiconductor transistors with fully surrounded active portions face high gate-source and gate-drain capacitances, which are inefficient and complex to implement.
Innovation Solution
A method for manufacturing transistors with parallel semiconductor nanofingers involves forming a single-crystal semiconductor layer, etching parallel walls, filling the gaps with insulating material, and coating with conductive material, while using thermal oxidation and annealing to optimize finger geometry and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon nanofinger is fully surrounded with a gate electrode, then the transistor can be controlled to on/off states, but the gate-source and gate-drain capacitances become high
Solution Approach 1:
The gate electrode is segmented into multiple parallel gates, each controlling a specific nanofinger channel. This segmentation allows the gate to control the transistor effectively while reducing the total capacitance by distributing the control across multiple smaller gates rather than one large surrounding gate.
Solution Approach 2:
The invention transitions from a three-dimensional fully surrounding gate structure to a planar parallel gate configuration. By changing the gate geometry from vertical/surrounding to horizontal/parallel, the capacitance between gate and source/drain is reduced while maintaining control effectiveness through the parallel arrangement.
2Reliability
If parallel walls are etched with width smaller than 100 nm, then the transistor efficiency is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent replaces conventional mechanical/chemical etching processes with self-organized nanofiber template guidance. The nanofibers act as natural masks that define the parallel wall positions and widths, eliminating the need for high-precision photolithography and etching alignment, thus achieving sub-100 nm dimensions with relaxed manufacturing precision requirements.
Solution Approach 2:
The nanofiber template automatically defines the geometry of parallel walls through its own structure. The self-organized nanofibers serve as their own positioning and dimensioning references, eliminating the need for external alignment systems and reducing manufacturing complexity while achieving the required sub-100 nm precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate-source and gate-drain capacitances, enhancing the efficiency and simplicity of transistor manufacturing by improving control over the transistor's on/off states.
Implementation Method 1
forming a single-crystal layer of a semiconductor material on a layer of an underlying material selectively etchable with respect to the single-crystal layer
Implementation Method 2
the coating with an insulator comprises a thermal oxidation
Implementation Method 3
the method comprises, before the step of filling with a conductive material, the step of performing an anneal to round the finger periphery
Data Source
AI summary
A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material.