Single Layer Nanofluidic Chip with NanoDLD Array
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Solution Overview
Problem
Conventional high-throughput nanofluidic processors require multiple layers or stacks of chips to manage fluid distribution and separation, leading to complexity and defects in bonding and fluid recombination, limiting their scalability and efficiency.
Innovation Solution
A single-layer nanofluidic chip with a nanoscale deterministic lateral displacement (nanoDLD) array integrated into a silicon wafer, using a housing structure with a top and bottom plate and spacer to create a clearance for fluid separation and drainage, allowing for parallel processing and efficient fluid management without the need for multiple layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple layers or stacks of chips are used to manage fluid distribution and separation, then fluid processing capability is improved, but device complexity and bonding defects increase
Solution Approach 1:
The patent merges multiple fluid distribution networks and separation functions into a single chip layer. The silicon wafer integrates input channel networks, output channel networks, and nanoDLD separator arrays all within one layer, eliminating the need for multiple stacked chips while maintaining high-throughput fluid processing capability.
Solution Approach 2:
The patent uses through-surface vias (TSVs) to create three-dimensional fluid pathways through the chip layer. This allows fluid networks to extend in the vertical dimension while remaining within a single chip plane, enabling complex fluid distribution without requiring multiple stacked layers.
2Productivity
If multiple layers or stacks of chips are used to manage fluid distribution and separation, then fluid processing capability is improved, but manufacturing defects increase
Solution Approach 1:
The patent combines all fluid distribution networks and separation functions into a single chip layer, eliminating the bonding processes between multiple layers. This single-layer integration removes the source of bonding defects while preserving high-throughput fluid processing capability.
3Adaptability or versatility
If conventional multilayer designs are used, then fluid distribution is achieved, but ease of manufacture decreases
Solution Approach 1:
The patent merges all fluid distribution networks into a single chip layer using standard semiconductor fabrication processes. This approach maintains versatile fluid distribution capability while significantly improving ease of manufacture by eliminating complex layer bonding and alignment procedures.
Solution Approach 2:
The patent employs through-surface vias to route fluid channels in the vertical dimension within a single chip layer. This enables complex three-dimensional fluid distribution networks to be manufactured using planar semiconductor fabrication techniques, greatly simplifying the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces complexity, enhances scalability, and achieves high-throughput fluid processing with precise colloidal separation, enabling the processing of larger volumes (up to 1-8 mL) in reasonable times, while preventing cross-contamination and improving the separation of challenging samples like extracellular vesicles.
Implementation Method 1
nanoscale deterministic lateral displacement arrays (nanoDLDs) to effect enrichment or separation of a sample
Data Source
AI summary
A fluidic processor device and a wafer including the same, the device including a nanofluidic separator chip including a nanoDLD array, a housing for housing the chip including a top plate disposed on a topside of the chip, a bottom plate disposed on a backside of the chip and fastened to the top plate, and a spacer disposed between the chip and the bottom plate to create a clearance between the chip and the bottom plate for forming a drain space on the backside of the chip.