Nanogap Sensor Readout with In-Sampling ADC and Smaller Capacitors
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Solution Overview
Problem
Conventional nanogap sensor systems face challenges in converting large full-scale currents to digital signals due to the need for large sampling capacitors, which occupy excessive chip surface area, and require extreme current attenuation, limiting the scalability and efficiency of nanogap sensor arrays.
Innovation Solution
The proposed solutions involve digitizing the signal as it is being sampled, allowing for short-term integration of a portion of the signal, reducing the size of sampling capacitors, and using digital counters for accumulation, which reduces the charge per quantization and eliminates the need for large capacitors, while also improving signal-to-noise ratio through digital decimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large sampling capacitors are used to convert full-scale currents to digital signals, then measurement precision is improved, but chip surface area is excessively occupied
Solution Approach 1:
The patent divides the signal processing into multiple stages: first stage performs initial sampling and quantization with smaller capacitors, second stage performs digital decimation and accumulation. This segmentation allows using smaller capacitors while maintaining overall measurement precision through multi-stage processing.
Solution Approach 2:
The patent replaces the traditional single-stage analog-to-digital conversion mechanism with a multi-stage system combining analog sampling, quantization, and digital signal processing. The digital decimation and accumulation stages substitute for the need for large analog sampling capacitors, reducing chip area while preserving measurement precision.
2Device complexity
If extreme current attenuation is applied to reduce full-scale currents, then signal processing is simplified, but signal-to-noise ratio deteriorates
Solution Approach 1:
The patent applies preliminary quantization to the current signal before digital processing stages. By quantizing the signal early in the pipeline, the system simplifies subsequent digital processing while maintaining signal integrity through proper quantization bit-depth selection, avoiding the need for extreme attenuation that would degrade signal-to-noise ratio.
Solution Approach 2:
The patent implements digital feedback mechanisms in the signal processing pipeline, where quantization results are fed back into digital decimation and accumulation stages. This feedback approach allows for controlled signal processing that maintains signal-to-noise ratio while simplifying overall system complexity through systematic digital processing.
3Measurement precision
If large sampling capacitors are used for signal integration, then measurement accuracy is improved, but manufacturing scalability is limited
Solution Approach 1:
The patent segments the signal integration function across multiple stages and devices. Instead of requiring one large capacitor per sensor, the system uses smaller capacitors in the first stage followed by digital accumulation across multiple quantization results. This segmentation enables manufacturing scalability while maintaining integration accuracy through distributed processing.
Solution Approach 2:
The patent uses digital copying and accumulation of quantization results instead of physical capacitor scaling. Multiple quantization measurements are digitally copied and accumulated to achieve the same integration accuracy that would require large physical capacitors, thereby enabling scalable manufacturing of sensor arrays.
4Ease of operation
If conventional analog-to-digital conversion is used, then signal processing is straightforward, but chip area and device complexity increase
Solution Approach 1:
The patent substitutes traditional analog-to-digital conversion mechanisms with a hybrid approach combining analog sampling, quantization, and digital signal processing. The digital decimation and accumulation stages replace the need for large analog processing components, reducing chip area while maintaining operational simplicity through systematic digital processing pipelines.
Solution Approach 2:
The patent changes the processing parameters from purely analog to a hybrid analog-digital approach. By introducing digital quantization and digital signal processing parameters (such as decimation factors and accumulation counts), the system reduces chip area requirements while maintaining ease of operation through programmable digital processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacture of smaller, commercially viable nanogap sensor arrays with millions of sensors by reducing the size of sampling capacitors and improving signal processing efficiency, allowing for more accurate and efficient molecular measurements.
Implementation Method 1
a relaxation oscillator, coupled to the readout input, for oscillating with an oscillation frequency indicative of the input signal
Implementation Method 2
sensors for evaluating analytes based on electron tunneling through a nanometric-sized gap between at least a pair of electrodes
Data Source
AI summary
Embodiments of the present disclosure relate to various methods and example systems for carrying out analog-to-digital conversion of data acquired by arrays of nanogap sensors. The nanogap sensors described herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes separated by a nanogap. In general, the methods and systems proposed herein rely on digitizing the signal as the signal is being integrated, and then integrating the digitized results. With such methods, the higher sample rate used in the digitizer reduces the charge per quantization and, therefore, the size of sampling capacitors used. Consequently, sampling capacitors may be made factors of magnitude smaller, requiring less valuable space on a chip compared to sampling capacitors used in conventional nanogap sensor arrays.