Nanoimprint Lithography Chip ID Encoding Wafer Location
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Solution Overview
Problem
Current methods for determining the original location of an IC chip on a wafer post-dicing are inefficient, as they often require additional steps, mechanical damage, or electrical read-outs, which can be costly and wasteful, especially for new technologies like low dielectric constant and flip chip architectures.
Innovation Solution
An optically readable chip ID is created using nanoimprint lithography, forming a hexadecimal pattern of indentations in an imprintable material on the IC chip, allowing for precise chip location identification prior to dicing, which can be read post-dicing without module builds or electrical read-outs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional electrical chip ID methods are used, then chip location identification can be achieved, but additional steps, mechanical damage, or electrical read-outs are required which increase cost and waste
Solution Approach 1:
The patent replaces electrical read-out systems with an optical system. Instead of using electrical probes or complex electrical circuits to read chip IDs, the invention uses optically readable markings (such as laser-marked patterns or color-coded features) that can be detected by simple optical sensors or cameras, thereby eliminating the need for complex electrical read-out infrastructure
Solution Approach 2:
The patent creates a visual copy or representation of chip location information through optically detectable markings on the chip itself. These markings serve as a visual record of the chip's original wafer location, allowing traceability without needing to access or read electrical circuits, thus simplifying the identification process
2Loss of information
If laser impingement is used to mark wafers, then unique wafer identification is provided, but it does not provide chip-level location identification post-dicing
Solution Approach 1:
The patent segments the wafer-level identification into chip-level identification. Instead of relying on a single wafer-wide marker, the invention creates unique identification markers on each individual chip that encode both the wafer ID and the specific chip's location coordinates on that wafer, enabling precise post-dicing traceability
Solution Approach 2:
The patent adds spatial dimensionality to the identification system by encoding X and Y coordinate information along with wafer ID. This transforms a two-dimensional wafer surface into a coordinate system where each chip's position can be precisely identified, adding the dimension of location precision to the identification process
3Reliability
If additional process steps are added for chip ID marking, then chip location identification is enabled, but manufacturing complexity and cost increase
Solution Approach 1:
The patent performs chip location identification marking as a preliminary action during the wafer fabrication process itself, before dicing. By incorporating the identification markers into the chip structure during manufacturing (using techniques like laser marking or inclusion of ID features in the chip design), the traceability information is established upfront without requiring separate post-dicing identification steps
Solution Approach 2:
The patent merges the chip location identification function with existing chip structures or manufacturing processes. Instead of adding a completely separate identification system, the invention integrates ID markers into the chip's existing features (such as using bond pad patterns, edge features, or laser-marking during normal fabrication), thereby enabling traceability without significantly increasing manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach avoids waste and costs associated with conventional electrical chip ID methods, enabling efficient and cost-effective chip location tracing post-dicing, suitable for various IC chip architectures, including new technologies.
Implementation Method 1
A curing process follows which provides an imprinted material that has a permanent optically readable ID disposed therein
Data Source
AI summary
An optically readable chip ID is provided to an imprintable material that is formed as a last level of an integrated circuit (IC) chip using nanoimprint lithography. The nanoimprint lithography process provides an array of indentations into the imprintable material that is typically arranged in a hexadecimal pattern. The hexadecimal pattern includes one or more optically readable characters which combine to encode chip location identification data. The chip location identification data identifies a unique location of the product chip on a wafer prior to dicing.