Printed Wiring Board Substrate Crack Testing by Nanoindentation

The patent applies preliminary action by pre-inducing cracks in the printed wiring board substrate through controlled indentation testing before conducting temperature cycle tests. This allows the identification of crack-prone locations in advance, enabling targeted monitoring during subsequent reliability tests. The preliminary indentation creates controlled stress concentrations that accelerate crack formation, thus reducing the time needed to observe reliability degradation patterns that would otherwise require months of temperature cycling to manifest.

The patent replaces the purely thermal-mechanical temperature cycle test with a combined mechanical indentation and thermal testing approach. By substituting part of the long-duration thermal stress application with direct mechanical indentation, the method accelerates crack initiation. The indentation test mechanically induces cracks that would otherwise require extensive thermal cycling to develop, thereby substituting mechanical action for prolonged thermal exposure and significantly reducing overall test time while maintaining reliability assessment validity.

The patent applies segmentation by dividing the multi-layer substrate into individual layers and analyzing each layer's contribution to overall stress and crack formation. The indentation testing method allows separate evaluation of crack resistance in each build-up layer, identifying which specific layers are most vulnerable to thermal expansion stress. This segmented approach enables targeted reinforcement or design modification of critical layers while maintaining the high integration achieved through multiple layers, thus resolving the contradiction between integration capability and substrate integrity.

The patent applies local quality by identifying specific locations and layers within the multi-layer substrate that are most susceptible to crack formation due to thermal expansion stress. The indentation testing reveals spatial variations in crack resistance across different layers and regions. This localized information allows for targeted design improvements, material selection, or stress relief features at critical locations rather than uniformly redesigning the entire multi-layer structure, thereby maintaining high integration while improving local substrate integrity where it matters most.