Nanolaminate Gate Stack for SiGe Substrates
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing gate current leakages due to defects at the interface between the semiconductor substrate and the gate oxide layer, particularly with the diffusion of elements like germanium, which are not effectively addressed by existing passivation layers or oxide bi-layer/tri-layer structures, leading to reliability issues and scaling limitations.
Innovation Solution
A nanolaminate structure is formed by alternately stacking first, second, and third metal oxide layers on a semiconductor substrate, which restricts the formation of germanium oxide and element diffusion, thereby improving interface trap density and reducing equivalent oxide thickness (EOT) to less than 1.5 nm, enhancing the scalability and reliability of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate oxide layer is used, then the device structure is simple, but interface trap density is high and gate current leakage occurs due to element diffusion
Solution Approach 1:
The gate oxide layer is segmented into multiple thin sub-layers (first oxide layer, second oxide layer, third oxide layer) with different materials and functions. Each sub-layer has a thickness of less than 1.5 nm, creating a nanolaminate structure that segments the protective function across multiple interfaces to prevent element diffusion while maintaining electrical performance.
Solution Approach 2:
The patent uses composite materials by combining different oxide materials (such as silicon oxide, silicon nitride, silicon oxynitride) in a layered nanolaminate structure. This composite approach leverages the complementary properties of each material to achieve both low interface trap density and effective diffusion barrier functionality.
2Length of moving object
If the oxide layer thickness is reduced to improve scaling, then device size decreases, but interface trap density increases and reliability deteriorates
Solution Approach 1:
Instead of using a single thin oxide layer that would have high interface trap density, the patent segments the thin oxide into multiple ultra-thin sub-layers. This segmentation creates additional interfaces that can be engineered to have low trap density, thereby maintaining reliability even as the total thickness is reduced for scaling.
Solution Approach 2:
Different regions of the gate oxide structure are assigned different local qualities through the use of different oxide materials in different layers. Each layer is optimized for specific local requirements (e.g., one layer for excellent interface quality, another for diffusion blocking), allowing the overall structure to achieve low interface trap density at reduced thickness.
3Reliability
If existing passivation layers are used to prevent element diffusion, then diffusion is partially blocked, but germanium oxide formation is not effectively restricted and interface trap density remains high
Solution Approach 1:
The patent employs a composite nanolaminate structure with specific oxide materials (silicon oxide, silicon nitride, silicon oxynitride) that work synergistically. This composite material approach provides superior diffusion blocking compared to conventional single-material passivation layers, while simultaneously achieving low interface trap density through the specific material组合 and interface engineering.
Solution Approach 2:
The nanolaminate structure acts as an intermediary between the semiconductor substrate and the gate electrode, providing multiple intermediate layers that progressively manage the interface quality and diffusion barriers. This intermediary structure is more effective than direct contact or single-layer passivation in preventing both germanium oxide formation and element diffusion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nanolaminate structure effectively decreases interface trap density and gate current leakages, allowing for further scaling down of semiconductor device sizes while maintaining high dielectric constants, thus addressing the limitations of existing solutions.
Implementation Method 1
The nanolaminate structure formed on the semiconductor substrate (e.g. a SiGe substrate or a Si substrate) helps to decrease defects in gate oxide layer-semiconductor substrate interfaces (i.e. a density of the interface trap) by restricting formation of oxides such as germanium oxide, and diffusion of elements in the semiconductor substrate
Data Source
AI summary
The present disclosure provides a method of forming a nanolaminate structure. First, a pre-treatment is performed on a semiconductor substrate, in which the semiconductor substrate includes SiGe. Then, a first metal oxide layer is formed on the semiconductor substrate. Then, at least one second metal oxide layer and at least one third metal oxide layer are alternately stacked on the first metal oxide layer, thereby forming a nanolaminate structure. And, a conductive gate layer is formed on the nanolaminate structure.