Nanolithographic Embedded Passive Device Manufacturing
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Solution Overview
Problem
Current nanolithographic techniques face challenges in reducing capacitor dielectric layer thickness below 100 nanometers, leading to limitations in capacitance and integration of high-capacitance capacitors at the nanometer scale, while also struggling with precise material placement and reliability in miniaturized microelectronic circuits.
Innovation Solution
Employing nanolithographic methods with metal-organic electrode materials and organo-ceramic dielectrics, introduced in a semi-solid form, which are printed onto substrates to form embedded passive devices with feature sizes less than 100 nanometers, using techniques like Dip Pen Nanolithography, and incorporating insulating ceramic layers to protect organic substrates, enabling precise control over electrode separation and dielectric layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional nanolithographic techniques are used to reduce dielectric layer thickness, then capacitance increases, but manufacturing precision deteriorates below 100 nanometers
Solution Approach 1:
The patent replaces conventional mechanical lithographic patterning methods with a self-assembly approach using block copolymers. The block copolymer system spontaneously forms nanoscale patterns through thermodynamic self-organization, eliminating the need for top-down mechanical patterning that loses precision below 100nm. This allows precise control of dielectric layer thickness at the nanoscale while maintaining manufacturing feasibility.
Solution Approach 2:
The patent changes the physical state and processing parameters of dielectric materials by using block copolymers that can be processed from solution and then thermally or chemically crosslinked. This parameter change enables precise thickness control through solution casting and self-assembly rather than mechanical deposition, achieving sub-100nm precision that was previously unattainable with conventional methods.
2Quantity of substance
If dielectric layer thickness is reduced to increase capacitance, then capacitance increases, but reliability deteriorates
Solution Approach 1:
The patent uses block copolymer composite materials consisting of different polymer blocks that self-assemble into ordered nanoscale structures. These composite materials provide both the thin dielectric layer needed for high capacitance and the structural integrity needed for reliability. The crosslinked network formed after processing creates a robust, defect-free dielectric layer that maintains reliability even at sub-100nm thicknesses.
Solution Approach 2:
The patent applies crosslinking treatment to the block copolymer dielectric layer before final device operation. This pre-treatment creates a crosslinked network that cushions against mechanical stress, electrical breakdown, and environmental degradation, preventing reliability issues that would normally occur in ultra-thin dielectric layers. The crosslinked structure provides inherent defect compensation and stress management.
3Ease of manufacture
If conventional lithographic methods are used, then manufacturing process is simpler, but feature size precision deteriorates at nanometer scale
Solution Approach 1:
The block copolymer system performs self-service by automatically forming precise nanoscale patterns through self-assembly without requiring complex external patterning equipment. The material itself contains the patterning information in its molecular structure, and it self-organizes into the desired geometry during processing. This eliminates the need for sophisticated lithographic tools while achieving superior precision.
Solution Approach 2:
The patent changes the processing parameters from mechanical deposition and patterning to solution-based self-assembly followed by crosslinking. This parameter change transforms a complex, equipment-intensive process into a simpler, chemistry-driven process that naturally achieves high precision through thermodynamic self-organization rather than mechanical control.
4Productivity
If capacitor size is reduced for integration, then integration density increases, but capacitance decreases
Solution Approach 1:
The patent exploits the vertical dimension by creating highly ordered multilayer structures through block copolymer self-assembly. The block copolymers form vertically stacked lamellae or cylindrical phases with precise nanoscale spacing, effectively utilizing the third dimension to pack more dielectric layers within a smaller footprint. This vertical stacking enables high integration density while maintaining or increasing total capacitance through multiple active interfaces.
Solution Approach 2:
The patent segments the capacitor structure into multiple thin dielectric layers separated by conductive blocks within the block copolymer architecture. This segmentation creates many small capacitor units stacked vertically, where each interface contributes to the total capacitance. The segmented structure allows high integration density on the substrate while the vertical stacking maintains high total capacitance through additive contribution of multiple layers.
Data Source
AI summary
A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.


