Nanomaterial T-Gate Transistors with Self-Aligned Doping
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Solution Overview
Problem
Conventional semiconductor devices, such as FETs, face challenges in reducing parasitic capacitance and improving high-frequency performance due to the limitations of traditional material and structural configurations.
Innovation Solution
The development of a nanostructure material (NSM) field effect transistor (FET) with a T-shaped gate electrode and a doping layer that is self-aligned, using materials like carbon nanotubes or graphene, which reduces parasitic capacitance and enhances high-frequency performance by optimizing the gate-source and gate-drain capacitances and resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional FET structures with planar gates are used, then manufacturing is simpler, but parasitic capacitance is higher and high-frequency performance deteriorates
Solution Approach 1:
The gate electrode is segmented into two distinct parts: a bottom gate electrode and an overhang gate electrode. This segmentation allows each gate component to be optimized independently for its specific function, reducing parasitic capacitance while maintaining manufacturability through separate formation steps.
Solution Approach 2:
The gate structure transitions from a conventional planar 2D configuration to a 3D T-shaped structure with vertical overhang components. This dimensional change enables the gate to extend over the source and drain regions, improving electrostatic control and reducing parasitic capacitance without significantly complicating the fabrication process.
2Manufacturing precision
If traditional doping methods are used, then doping coverage is limited to horizontal regions, but access resistance remains high and capacitance control is insufficient
Solution Approach 1:
The doping layer extends vertically along the sidewalls of the gate electrode in addition to horizontal coverage. This 3D doping configuration enables precise control of doping coverage in both planar and vertical dimensions, reducing access resistance while maintaining proper capacitance control through self-aligned formation.
Solution Approach 2:
The doping layer is formed in a self-aligned manner where the gate electrode structure itself defines the doping region boundaries. This self-alignment eliminates the need for additional alignment steps and ensures precise doping coverage control without increasing manufacturing complexity.
3Reliability
If NSM layers are used, then high-frequency performance is improved, but parasitic capacitance requires additional structural optimization
Solution Approach 1:
The T-shaped gate electrode and doping layer form a self-aligned structure where each component automatically defines the boundaries of the other. This self-alignment reduces the need for additional fabrication steps and alignment procedures, minimizing device complexity while achieving the required parasitic capacitance reduction for high-frequency performance.
Data Source
AI summary
A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.