Gate-First Nanomesh FET Processing for Current Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nanowire field effect transistors face challenges in current density per unit device area and complex processing steps, particularly in forming replacement gate structures, which increase processing time and manufacturing cost.
Innovation Solution
A gate-first processing scheme for forming a nanomesh field effect transistor involves patterning an alternating stack of semiconductor materials, etching to form suspended nanowires, forming a gate dielectric and electrode structure, and using selective epitaxy to create thickened source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replacement gate structure is used in nanowire field effect transistors, then device performance is improved, but processing complexity increases
Solution Approach 1:
The patent inverts the conventional gate formation sequence by forming the gate electrode structure before the nanowire channels (gate-first approach), whereas traditionally nanowires are formed first followed by gate structures (replacement gate). This inversion eliminates the need for complex replacement gate processing steps while maintaining device performance, directly resolving the contradiction between device performance and processing complexity
2Reliability
If replacement gate structure is used in nanowire field effect transistors, then device performance is improved, but manufacturing cost increases
Solution Approach 1:
By inverting the gate formation sequence to gate-first approach, the patent eliminates the need for additional complex processing steps required for replacement gate structures, thereby reducing manufacturing cost while maintaining the improved device performance that replacement gate would have provided
3Productivity
If conventional nanowire field effect transistor processing is used, then processing steps are simpler, but current density per unit device area is reduced
Solution Approach 1:
The gate-first approach inverts the conventional processing sequence, enabling the formation of optimized gate electrode structures that enhance current density per unit device area. This inversion achieves higher productivity without significantly increasing processing complexity, as it eliminates the need for replacement gate steps while maintaining structural simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the processing steps, enhances current density, and reduces manufacturing costs by eliminating the need for additional processing steps associated with replacement gate structures.
Implementation Method 1
The second semiconductor material is removed selective to the first semiconductor material
Implementation Method 2
A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh
Implementation Method 3
An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack
Implementation Method 4
A selective epitaxy process can be employed to form a source region and a drain region
Data Source
AI summary
A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.


