Nanomesh SRAM Cell Layout Density and Process Variation Control
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Solution Overview
Problem
Conventional SRAM designs face challenges in minimizing process variations due to non-linear edges in active area and gate definition masks, leading to performance issues in layout density and device consistency.
Innovation Solution
The use of nanowire-based SRAM cells with pass gates and inverters, where each device layer includes source and drain regions doped with n-type and p-type dopants, and a common gate surrounding nanowire channels, allows for the formation of a gridded configuration that reduces lithography variations and maximizes layout density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional SRAM designs use non-linear edges in active area and gate definition masks to increase layout density, then layout density is improved, but process variations in lithography and etching increase leading to performance degradation
Solution Approach 1:
The SRAM cell is divided into multiple device layers (first device layer and second device layer) with each layer containing specific transistors. This segmentation allows different portions of the circuit to be fabricated in separate layers, enabling the use of regular linear patterns in each layer while achieving high overall density through vertical stacking.
Solution Approach 2:
The patent transitions from planar 2D layout to 3D vertical stacking by introducing multiple device layers. The first device layer and second device layer are stacked vertically, allowing high layout density to be achieved through the third dimension rather than through complex non-linear 2D patterns that suffer from process variations.
2Productivity
If conventional SRAM designs adjust layout to minimize cell size, then layout density is improved, but the device becomes more sensitive to lithography, etching and process variations
Solution Approach 1:
By segmenting the SRAM cell into multiple device layers with distinct transistor assignments, the design achieves high density without requiring extreme miniaturization of individual features. Each layer can be optimized independently, reducing sensitivity to process variations while maintaining small overall cell footprint.
Solution Approach 2:
Different device layers are assigned different transistor types and configurations optimized for their specific functions. The first device layer contains specific transistors while the second device layer contains others, allowing each layer to be locally optimized for its role while contributing to overall high density and robustness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nanowire-based SRAM design achieves reduced process variations and increased layout density through regular patterns, enhancing the consistency and performance of SRAM cells by aligning all features uniformly, thus improving device reliability.
Implementation Method 1
the source and drain regions of one or more of the pass gate device layers are doped with at least one n-type dopant, and the source and drain regions of one or more of the inverter device layers are doped with at least one n-type dopant and the source and drain regions of one or more other of the inverter device layers are doped with at least one p-type dopant
Data Source
AI summary
Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.