Nanomolded Semiconductor Interconnects With Crystallinity Control
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Solution Overview
Problem
Current nanofabrication techniques struggle to simultaneously control crystallinity, size, morphology, and material composition for nanostructure interconnects in semiconductor devices, limiting their efficiency and operational speed due to limitations in material choice, substrate dependency, and complexity in forming high-aspect-ratio structures.
Innovation Solution
A method involving thermomechanical nanomolding (TMNM) is used to form semiconductor interconnects by establishing a nanostructure in a substrate and performing a thermal process to mold an electrically conductive material into the nanostructure, allowing for the creation of high-aspect-ratio single crystal nanowires and enabling control over crystallinity, size, and material composition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If bottom-up techniques such as molecular beam epitaxy and atomic layer deposition are used, then high quality single crystalline films and coatings can be fabricated, but the techniques are generally not useful in the fabrication of other more complex nanostructures and require extensive optimization for each material composition
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming the nanoporous mold structure, depositing the material composition, and applying thermal/pressure treatment. This segmentation allows each stage to be optimized independently, enabling control over crystallinity while accommodating various material compositions through the standardized mold-based approach.
Solution Approach 2:
A nanoporous mold structure serves as an intermediary between the substrate and the final nanostructure. This mold acts as a template that guides the formation of complex nanostructures with controlled crystallinity, while the material composition can be varied by changing the deposit material without requiring reoptimization of the entire fabrication process.
2Manufacturing precision
If colloidal synthesis techniques are used, then acceptable size, shape, and composition control can be achieved, but the techniques are generally limited to 0D or 1D nanostructures and require surface ligands to stabilize in solution
Solution Approach 1:
The nanoporous mold structure serves as an intermediary template that enables the formation of 2D and 3D nanostructures, overcoming the dimensionality limitation of colloidal synthesis. The mold provides physical constraints that guide material deposition into complex geometries without requiring surface ligands, while still maintaining acceptable size and shape control.
Solution Approach 2:
The chemical stabilization mechanism using surface ligands is replaced with a mechanical confinement approach using the nanoporous mold. The mold's physical structure provides the necessary constraints for size and shape control, eliminating the need for surface ligands and enabling broader nanostructure dimensionality.
3Area of stationary object
If interconnect size is reduced to nano-scale, then the footprint of electrical devices can shrink, but challenges arise in design and fabrication due to limitations in operational speed and efficiency
Solution Approach 1:
The approach changes the crystalline structure parameter of the interconnect material by using controlled thermal processing after deposition. This induces crystallinity in the nano-scale interconnects, which improves electrical conductivity and operational speed, thereby maintaining performance despite the reduced size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of efficient semiconductor interconnects with precise control over crystallinity and morphology, enhancing the operational speed and efficiency of semiconductor devices by creating high-aspect-ratio nanostructures that can connect semiconductor structures effectively.
Implementation Method 1
performing a thermal process on the semiconductor assembly that causes the electrically conductive material to mold into the nanostructure established in the substrate
Data Source
AI summary
A method for forming semiconductor interconnects includes establishing a nanostructure in a substrate. The nanostructure may be embodied as a trench or other structure that extends from a first semiconductor device or structure to a second semiconductor device or structure. The method also includes establishing an electrically conductive material, such as a polycrystalline or single crystal copper material, on the substrate over the nanostructure to form a semiconductor assembly. The semiconductor assembly is then subjected to thermal process that causes the electrically conductive material to mold into the nanostructure established in the substrate to form an electrical interconnect that electrically connects the first semiconductor structure to the second semiconductor structure.