Nanoporous Semiconductor via Metal-Assisted Etching

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Solution Overview

Problem

Current nanofabrication techniques are limited in producing nanoporous semiconductor materials with finely controlled morphology and scalability, particularly in achieving smaller pore sizes, smaller inter-pore spacing, and larger pore aspect ratios, while being cost-effective and suitable for larger device sizes.

Innovation Solution

The method involves positioning nanoparticles with a noble metal core and a sacrificial spacer layer onto a semiconductor substrate, allowing them to self-assemble into a close-packed array, and then removing the sacrificial layer to form spaced noble metal nanoparticles that catalyze etching, creating nanopores with controlled sizes and spacing through a metal-assisted chemical etching process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional nanofabrication techniques are used, then nanoporous semiconductor materials can be produced, but the pore sizes, inter-pore spacing, and aspect ratios are limited and cannot achieve sub-10 nm precision

Engineering Contradiction:
Improvepore size controlVSAvoidfabrication complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent uses sacrificial nanoparticle templates (comprising a core and spacer layer) as intermediaries to define pore geometry. These templates self-assemble on the semiconductor substrate and guide the etching process, enabling precise sub-10 nm pore formation without requiring complex lithography tools. The sacrificial material is later removed to create the final porous structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The nanoparticle template is segmented into two functional parts: a core component that defines the pore location and a sacrificial spacer layer that controls the inter-pore spacing. This segmentation allows independent optimization of pore size and spacing parameters, achieving precise control over both characteristics simultaneously.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If nanoporous semiconductor materials with smaller pore sizes and smaller inter-pore spacing are produced, then the material performance improves, but the manufacturing scalability decreases

Engineering Contradiction:
Improveinter-pore spacing controlVSAvoidmanufacturing scalability
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The nanoparticle templates self-assemble into ordered arrays on the semiconductor substrate through spontaneous organization, eliminating the need for complex alignment and positioning equipment. This self-assembly mechanism enables scalable production of uniformly spaced nanopores across large substrate areas, maintaining precision while improving productivity.

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If larger pore aspect ratios are achieved, then the material performance improves, but the etching homogeneity deteriorates

Engineering Contradiction:
Improvepore aspect ratioVSAvoidetching homogeneity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The etching process is localized to the immediate vicinity of each nanoparticle template, creating vertically oriented pores with high aspect ratios. The confined etching zone around each template ensures uniform pore formation even at high aspect ratios, maintaining etching homogeneity while achieving the desired pore geometry.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the production of nanoporous semiconductor materials with sub-10 nm pore diameters, high pore aspect ratios, and increased porosity, improving scalability and etching homogeneity, and is suitable for larger device sizes and high-throughput manufacturing.

Implementation Method 1

forming a plurality of pores in the semiconductor material by etching the semiconductor surface at a location of at least a portion of the plurality of spaced noble metal nanoparticles

Methodology Applied
Scientific EffectCatalysis: Catalysis

Implementation Method 2

assembling at least a portion of the nanoparticles comprising a noble metal core and a sacrificial spacer layer surrounding the noble metal core into a close-packed array

Methodology Applied
Scientific EffectSelf-assembly: Self-Assembly

Data Source

PatentUS10943982B2Nanoporous semiconductor materials
Publication Date: 2021.03.09 MASSACHUSETTS INST OF TECH
  • US10943982B2 patent drawing
  • US10943982B2 patent drawing
  • US10943982B2 patent drawing

AI summary

Methods for forming nanoporous semiconductor materials are described. The methods allow for the formation of micron-scale arrays of sub-10nm nanopores in semiconductor materials with narrow size distributions and aspect ratios of over 400:1.