3D Nanoribbon SRAM Vertical Stacking Density
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Solution Overview
Problem
Conventional memory technologies face challenges in increasing memory density due to limitations in the number of transistors that can be formed on a semiconductor substrate, leading to diminishing returns and increased complexity and cost in scaling memory cells.
Innovation Solution
The use of semiconductor nanoribbons stacked vertically to create high-density three-dimensional (3D) static random-access memory (SRAM) cells, allowing for independent gate control and integration of transistors in upper metal layers, which reduces the footprint and enhances memory density while simplifying integration with advanced CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory scaling is used to increase memory density, then memory capacity increases, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell arrangement to three-dimensional (3D) vertically stacked nanoribbon structures. Multiple memory layers are stacked vertically above each other, utilizing the third dimension (height) to increase memory density without proportionally increasing the substrate footprint or manufacturing complexity. This dimensional change allows multiple memory cells to occupy the same planar area through vertical stacking.
2Quantity of substance
If more transistors are integrated per substrate area to increase memory density, then memory capacity increases, but control over individual memory cells deteriorates
Solution Approach 1:
The patent divides the memory structure into segmented nanoribbons, where each nanoribbon can be independently controlled by its own gate electrode. This segmentation allows individual memory cells or groups of cells to be controlled separately, maintaining ease of operation even as memory density increases through vertical stacking. Each nanoribbon acts as an independent conduction path with dedicated control.
Solution Approach 2:
The patent implements local gate control where each nanoribbon has its own gate electrode that can be independently biased. This local quality approach allows different regions of the memory structure to be controlled independently, enabling selective access to specific memory cells while maintaining overall high density through the vertical arrangement.
3Quantity of substance
If planar memory expansion is used to increase capacity, then memory density increases, but substrate area requirements increase
Solution Approach 1:
The patent utilizes vertical stacking of multiple memory layers in the third dimension, allowing memory capacity to increase without proportionally increasing the substrate footprint. The vertically stacked nanoribbon structure enables multiple memory cells to occupy the same planar area, effectively transitioning from 2D planar expansion to 3D vertical expansion.
Data Source
AI summary
Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density 3D SRAM. An example device includes an SRAM cell built based on a first nanoribbon, suitable for forming NMOS transistors, and a second nanoribbon, suitable for forming PMOS transistors. Both nanoribbons may extend substantially in the same plane above a support structure over which the memory device is provided. The SRAM cell includes transistors M1-M4, arranged to form two inverter structures. The first inverter structure includes transistor M1 in the first nanoribbon and transistor M2 in the second nanoribbon, while the second inverter structure includes transistor M3 in the first nanoribbon and transistor M4 in the second nanoribbon. The IC device may include multiple layers of nanoribbons, with one or more such SRAM cells in each layer, stacked upon one another above the support structure, thus realizing 3D SRAM.