Insulator-Filled Trenches for Nanoribbon Transistor Alignment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing methods for forming registration marks for nanoribbon-based transistors are costly and time-consuming, and the resulting marks are often ineffective for aligning subsequent processes due to lack of detectability after deposition of semiconductor layers.

Innovation Solution

The use of patterned trenches in the substrate, filled with an insulator material, serves as registration marks for nanoribbon-based transistor alignment, allowing for precise alignment of implant and subsequent processes without the need for expensive polysilicon regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If polysilicon regions are used for registration marks, then alignment precision is improved, but manufacturing cost and process time increase

Engineering Contradiction:
Improvealignment precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts the registration mark function from the expensive polysilicon material and implements it using simple insulator-filled trenches. The trenches are etched into the substrate and filled with insulator material, creating detectable registration marks without requiring polysilicon deposition processes.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses inexpensive insulator material to create registration marks that serve their alignment purpose throughout the fabrication process. These trench-based marks provide a cost-effective alternative to expensive polysilicon regions while maintaining detectability.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Manufacturing precision

If polysilicon regions are used for registration marks, then alignment precision is improved, but fabrication time increases

Engineering Contradiction:
Improvealignment precisionVSAvoidfabrication throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent removes the time-consuming polysilicon deposition step from the registration mark formation process. By using insulator-filled trenches instead, the registration marks can be created using standard etching and filling processes that are already part of the fabrication workflow, thereby improving throughput.

Inventive Principle:
Principle #2Taking out (Extraction)

3Manufacturing precision

If registration marks are formed before implant, then alignment is enabled, but detectability is lost after semiconductor layer deposition

Engineering Contradiction:
Improvealignment capabilityVSAvoiddetectability
Core Design Contradiction:
Manufacturing precisionVSDifficulty of detecting and measuring

Solution Approach 1:

The patent performs the trench formation and insulator filling before semiconductor layer deposition, creating permanent structural features in the substrate. These pre-formed trenches maintain their detectability throughout subsequent processing because they are etched into the substrate itself rather than being surface-level marks that get buried.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250386564A1Patterned trenches for nanoribbon-based transistor registration and alignment
Publication Date: 2025.12.18 INTEL CORP
  • US20250386564A1 patent drawing
  • US20250386564A1 patent drawing
  • US20250386564A1 patent drawing

AI summary

A method of fabricating an integrated circuit (IC) structure including patterned trenches for nanoribbon-based transistors for registration and alignment may involve etching an opening in a substrate, where the opening may be used for alignment of an implant process. Instead of filling the opening (e.g., with polysilicon), after implant, a stack of alternate layers of semiconductor materials may be provided both over the substrate and in the opening. The method may then involve patterning the stack into fins, where patterning the stack involves removing the semiconductor material from the opening. The opening may then be filled with an insulator material, and nanoribbon-based transistors may be formed from the fins. In one example, the resulting IC structure includes an insulator-filled trench in the substrate in a plane below the nanoribbon stacks.