Nanoribbon Width Modulation for SRAM Read Stability
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Solution Overview
Problem
Conventional SRAM bit-cells require significant chip area for read assist circuitry to mitigate read disturbance, which increases overhead and reduces SRAM read efficiency.
Innovation Solution
Implementing SRAM bit-cells with pass-gate transistors having narrower nanoribbon widths compared to pull-down transistors, reducing drive current and thereby minimizing the need for read assist circuitry, achieved through nanoribbon width modulation between pass-gate and pull-down transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read assist circuitry is added to mitigate read disturbance, then read stability is improved, but chip area increases and read efficiency decreases
Solution Approach 1:
The patent applies local quality by modulating the nanoribbon width specifically in the pass-gate transistor channel region to be narrower than in other regions. This localized geometric modification reduces the drive current of the pass-gate transistor, thereby reducing read disturbance to the storage node while maintaining the overall functionality of the SRAM bit-cell without requiring additional read assist circuitry.
Solution Approach 2:
The patent changes the geometric parameter of the nanoribbon width to control the electrical characteristics of the pass-gate transistor. By reducing the nanoribbon width in the pass-gate channel, the drive current is reduced, which mitigates read disturbance and improves read stability without increasing chip area.
2Reliability
If read assist circuitry is added to mitigate read disturbance, then read stability is improved, but read efficiency decreases
Solution Approach 1:
The patent applies local quality by modulating the nanoribbon width specifically in the pass-gate transistor channel region to be narrower than in other regions. This localized geometric modification reduces the drive current of the pass-gate transistor, thereby reducing read disturbance to the storage node while maintaining the overall functionality of the SRAM bit-cell without requiring additional read assist circuitry.
Solution Approach 2:
The patent changes the geometric parameter of the nanoribbon width to control the electrical characteristics of the pass-gate transistor. By reducing the nanoribbon width in the pass-gate channel, the drive current is reduced, which mitigates read disturbance and improves read stability without increasing chip area.
3Object-generated harmful factors
If nanoribbon width is reduced in pass-gate transistor, then read disturbance is reduced, but drive current of pass-gate transistor decreases
Solution Approach 1:
The patent applies local quality by modulating the nanoribbon width specifically in the pass-gate transistor channel region to be narrower than in other regions. This localized geometric modification reduces the drive current of the pass-gate transistor, thereby reducing read disturbance to the storage node while maintaining the overall functionality of the SRAM bit-cell without requiring additional read assist circuitry.
Solution Approach 2:
The patent changes the geometric parameter of the nanoribbon width to control the electrical characteristics of the pass-gate transistor. By reducing the nanoribbon width in the pass-gate channel, the drive current is reduced, which mitigates read disturbance and improves read stability without increasing chip area.
Data Source
AI summary
Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.